; ModuleID = './wiring_analog.c' target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-i64:8:8-f32:8:8-f64:8:8-n8" target triple = "avr" @analog_reference = global i8 1, align 1 @digital_pin_to_timer_PGM = external constant [0 x i8], align 1 ; Function Attrs: nounwind define void @analogReference(i8 zeroext %mode) #0 { entry: store i8 %mode, i8* @analog_reference, align 1, !tbaa !1 ret void } ; Function Attrs: nounwind define i16 @analogRead(i8 zeroext %pin) #0 { entry: %cmp = icmp ugt i8 %pin, 13 %sub = add i8 %pin, 2 %sub.pin = select i1 %cmp, i8 %sub, i8 %pin %0 = load i8, i8* @analog_reference, align 1, !tbaa !1 %shl = shl i8 %0, 6 %and = and i8 %sub.pin, 7 %or = or i8 %shl, %and store volatile i8 %or, i8* inttoptr (i16 124 to i8*), align 4, !tbaa !1 %1 = load volatile i8, i8* inttoptr (i16 122 to i8*), align 2, !tbaa !1 %or8 = or i8 %1, 64 store volatile i8 %or8, i8* inttoptr (i16 122 to i8*), align 2, !tbaa !1 br label %while.cond while.cond: ; preds = %while.cond, %entry %2 = load volatile i8, i8* inttoptr (i16 122 to i8*), align 2, !tbaa !1 %and11 = and i8 %2, 64 %tobool = icmp eq i8 %and11, 0 br i1 %tobool, label %while.end, label %while.cond while.end: ; preds = %while.cond %3 = load volatile i8, i8* inttoptr (i16 120 to i8*), align 8, !tbaa !1 %4 = load volatile i8, i8* inttoptr (i16 121 to i8*), align 1, !tbaa !1 %conv12 = zext i8 %4 to i16 %shl13 = shl nuw i16 %conv12, 8 %conv14 = zext i8 %3 to i16 %or15 = or i16 %shl13, %conv14 ret i16 %or15 } ; Function Attrs: nounwind define void @analogWrite(i8 zeroext %pin, i16 %val) #0 { entry: tail call void @pinMode(i8 zeroext %pin, i8 zeroext 1) #2 switch i16 %val, label %if.else.3 [ i16 0, label %if.then i16 255, label %if.then.2 ] if.then: ; preds = %entry tail call void @digitalWrite(i8 zeroext %pin, i8 zeroext 0) #2 br label %if.end.37 if.then.2: ; preds = %entry tail call void @digitalWrite(i8 zeroext %pin, i8 zeroext 1) #2 br label %if.end.37 if.else.3: ; preds = %entry %conv = zext i8 %pin to i16 %add.ptr = getelementptr inbounds [0 x i8], [0 x i8]* @digital_pin_to_timer_PGM, i16 0, i16 %conv %0 = ptrtoint i8* %add.ptr to i16 %1 = tail call i8 asm sideeffect "lpm\0A\09mov $0, r0\0A\09", "=r,z,~{r0}"(i16 %0) #2, !srcloc !4 switch i8 %1, label %sw.default [ i8 1, label %sw.bb i8 2, label %sw.bb.8 i8 3, label %sw.bb.13 i8 4, label %sw.bb.17 i8 7, label %sw.bb.21 i8 8, label %sw.bb.26 ] sw.bb: ; preds = %if.else.3 %2 = load volatile i8, i8* inttoptr (i16 68 to i8*), align 4, !tbaa !1 %or = or i8 %2, -128 store volatile i8 %or, i8* inttoptr (i16 68 to i8*), align 4, !tbaa !1 %conv7 = trunc i16 %val to i8 store volatile i8 %conv7, i8* inttoptr (i16 71 to i8*), align 1, !tbaa !1 br label %if.end.37 sw.bb.8: ; preds = %if.else.3 %3 = load volatile i8, i8* inttoptr (i16 68 to i8*), align 4, !tbaa !1 %or10 = or i8 %3, 32 store volatile i8 %or10, i8* inttoptr (i16 68 to i8*), align 4, !tbaa !1 %conv12 = trunc i16 %val to i8 store volatile i8 %conv12, i8* inttoptr (i16 72 to i8*), align 8, !tbaa !1 br label %if.end.37 sw.bb.13: ; preds = %if.else.3 %4 = load volatile i8, i8* inttoptr (i16 128 to i8*), align 128, !tbaa !1 %or15 = or i8 %4, -128 store volatile i8 %or15, i8* inttoptr (i16 128 to i8*), align 128, !tbaa !1 store volatile i16 %val, i16* inttoptr (i16 136 to i16*), align 8, !tbaa !5 br label %if.end.37 sw.bb.17: ; preds = %if.else.3 %5 = load volatile i8, i8* inttoptr (i16 128 to i8*), align 128, !tbaa !1 %or19 = or i8 %5, 32 store volatile i8 %or19, i8* inttoptr (i16 128 to i8*), align 128, !tbaa !1 store volatile i16 %val, i16* inttoptr (i16 138 to i16*), align 2, !tbaa !5 br label %if.end.37 sw.bb.21: ; preds = %if.else.3 %6 = load volatile i8, i8* inttoptr (i16 176 to i8*), align 16, !tbaa !1 %or23 = or i8 %6, -128 store volatile i8 %or23, i8* inttoptr (i16 176 to i8*), align 16, !tbaa !1 %conv25 = trunc i16 %val to i8 store volatile i8 %conv25, i8* inttoptr (i16 179 to i8*), align 1, !tbaa !1 br label %if.end.37 sw.bb.26: ; preds = %if.else.3 %7 = load volatile i8, i8* inttoptr (i16 176 to i8*), align 16, !tbaa !1 %or28 = or i8 %7, 32 store volatile i8 %or28, i8* inttoptr (i16 176 to i8*), align 16, !tbaa !1 %conv30 = trunc i16 %val to i8 store volatile i8 %conv30, i8* inttoptr (i16 180 to i8*), align 4, !tbaa !1 br label %if.end.37 sw.default: ; preds = %if.else.3 %cmp32 = icmp slt i16 %val, 128 br i1 %cmp32, label %if.then.34, label %if.else.35 if.then.34: ; preds = %sw.default tail call void @digitalWrite(i8 zeroext %pin, i8 zeroext 0) #2 br label %if.end.37 if.else.35: ; preds = %sw.default tail call void @digitalWrite(i8 zeroext %pin, i8 zeroext 1) #2 br label %if.end.37 if.end.37: ; preds = %if.then.2, %if.then.34, %if.else.35, %sw.bb.26, %sw.bb.21, %sw.bb.17, %sw.bb.13, %sw.bb.8, %sw.bb, %if.then ret void } declare void @pinMode(i8 zeroext, i8 zeroext) #1 declare void @digitalWrite(i8 zeroext, i8 zeroext) #1 attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="atmega328p" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="atmega328p" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } !llvm.ident = !{!0} !0 = !{!"clang version 3.7.0 (https://github.com/llvm-mirror/clang.git 287e62c84a1ccd74fbca46bfc13e364e314d4b41) (https://github.com/llvm-mirror/llvm.git aaab572fc38b4438e769e2fd6b91963be11db7b2)"} !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} !3 = !{!"Simple C/C++ TBAA"} !4 = !{i32 -2147149877, i32 -2147149868, i32 -2147149827} !5 = !{!6, !6, i64 0} !6 = !{!"short", !2, i64 0}