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Created April 11, 2023 12:13
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PowerPC ISA 3.1B Instructions
Raw
README.md

isa.json (v1)

These instructions were extracted from the public PowerPC 3.1B ISA (September 14, 2021).

More work to follow on extracting the descriptions with correct fomatting and fix any issues found in the current data.

Raw
isa.json
{
"instructions": [
{
"assembly": [
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"encoding": [
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},
{
"name": "AA",
"offset": 30,
"size": 1
},
{
"name": "LK",
"offset": 31,
"size": 1
}
],
"heading": "Branch I-form",
"texts": [
"b target_addr (AA=0 LK=0)",
"ba target_addr (AA=1 LK=0)",
"bl target_addr (AA=0 LK=1)",
"bla target_addr (AA=1 LK=1)"
]
}
],
"extended_mnemonics": [],
"page": 67
},
{
"assembly": [
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"encoding": [
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"name": "16",
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"size": 5
},
{
"name": "BD",
"offset": 16,
"size": 14
},
{
"name": "AA",
"offset": 30,
"size": 1
},
{
"name": "LK",
"offset": 31,
"size": 1
}
],
"heading": "Branch Conditional B-form",
"texts": [
"bc BO,BI,target_addr (AA=0 LK=0)",
"bca BO,BI,target_addr (AA=1 LK=0)",
"bcl BO,BI,target_addr (AA=0 LK=1)",
"bcla BO,BI,target_addr (AA=1 LK=1)"
]
}
],
"extended_mnemonics": [
"blt target bc 12,0,target",
"bne cr2,target bc 4,10,target",
"bdnz target bc 16,0,target"
],
"page": 67
},
{
"assembly": [
{
"encoding": [
{
"name": "19",
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},
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"size": 3
},
{
"name": "BH",
"offset": 19,
"size": 2
},
{
"name": "16",
"offset": 21,
"size": 10
},
{
"name": "LK",
"offset": 31,
"size": 1
}
],
"heading": "Branch Conditional to Link Register XL-form",
"texts": [
"bclr BO,BI,BH (LK=0)",
"bclrl BO,BI,BH (LK=1)"
]
}
],
"extended_mnemonics": [
"bclr 4,6 bclr 4,6,0",
"bltlr bclr 12,0,0",
"bnelr cr2 bclr 4,10,0",
"bdnzlr bclr 16,0,0"
],
"page": 68
},
{
"assembly": [
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"encoding": [
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"name": "19",
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"size": 5
},
{
"name": "///",
"offset": 16,
"size": 3
},
{
"name": "BH",
"offset": 19,
"size": 2
},
{
"name": "528",
"offset": 21,
"size": 10
},
{
"name": "LK",
"offset": 31,
"size": 1
}
],
"heading": "Branch Conditional to Count Register XL-form",
"texts": [
"bcctr BO,BI,BH (LK=0)",
"bcctrl BO,BI,BH (LK=1)"
]
}
],
"extended_mnemonics": [
"bcctr 4,6 bcctr 4,6,0",
"bltctr bcctr 12,0,0",
"bnectr cr2 bcctr 4,10,0"
],
"page": 68
},
{
"assembly": [
{
"encoding": [
{
"name": "19",
"offset": 0,
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},
{
"name": "///",
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"size": 3
},
{
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"size": 2
},
{
"name": "560",
"offset": 21,
"size": 10
},
{
"name": "LK",
"offset": 31,
"size": 1
}
],
"heading": "Branch Conditional to Branch Target Address Register XL-form",
"texts": [
"bctar BO,BI,BH (LK=0)",
"bctarl BO,BI,BH (LK=1)"
]
}
],
"extended_mnemonics": [],
"page": 69
},
{
"assembly": [
{
"encoding": [
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"name": "19",
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{
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"size": 5
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"size": 5
},
{
"name": "BB",
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"size": 5
},
{
"name": "257",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register AND XL-form",
"texts": [
"crand BT,BA,BB"
]
}
],
"extended_mnemonics": [],
"page": 70
},
{
"assembly": [
{
"encoding": [
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{
"name": "449",
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"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register OR XL-form",
"texts": [
"cror BT,BA,BB"
]
}
],
"extended_mnemonics": [
"crmove Bx,By cror Bx,By,By"
],
"page": 70
},
{
"assembly": [
{
"encoding": [
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"name": "19",
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},
{
"name": "225",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register NAND XL-form",
"texts": [
"crnand BT,BA,BB"
]
}
],
"extended_mnemonics": [],
"page": 70
},
{
"assembly": [
{
"encoding": [
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"size": 5
},
{
"name": "BB",
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"size": 5
},
{
"name": "193",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register XOR XL-form",
"texts": [
"crxor BT,BA,BB"
]
}
],
"extended_mnemonics": [
"crclr Bx crxor Bx,Bx,Bx"
],
"page": 70
},
{
"assembly": [
{
"encoding": [
{
"name": "19",
"offset": 0,
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{
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{
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"size": 5
},
{
"name": "BB",
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},
{
"name": "33",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register NOR XL-form",
"texts": [
"crnor BT,BA,BB"
]
}
],
"extended_mnemonics": [
"crnot Bx,By crnor Bx,By,By"
],
"page": 71
},
{
"assembly": [
{
"encoding": [
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{
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"size": 5
},
{
"name": "BB",
"offset": 16,
"size": 5
},
{
"name": "129",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register AND with Complement XL-form",
"texts": [
"crandc BT,BA,BB"
]
}
],
"extended_mnemonics": [],
"page": 71
},
{
"assembly": [
{
"encoding": [
{
"name": "19",
"offset": 0,
"size": 6
},
{
"name": "BT",
"offset": 6,
"size": 5
},
{
"name": "BA",
"offset": 11,
"size": 5
},
{
"name": "BB",
"offset": 16,
"size": 5
},
{
"name": "289",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register Equivalent XL-form",
"texts": [
"creqv BT,BA,BB"
]
}
],
"extended_mnemonics": [
"crset Bx creqv Bx,Bx,Bx"
],
"page": 71
},
{
"assembly": [
{
"encoding": [
{
"name": "19",
"offset": 0,
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{
"name": "BT",
"offset": 6,
"size": 5
},
{
"name": "BA",
"offset": 11,
"size": 5
},
{
"name": "BB",
"offset": 16,
"size": 5
},
{
"name": "417",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Condition Register OR with Complement XL-form",
"texts": [
"crorc BT,BA,BB"
]
}
],
"extended_mnemonics": [],
"page": 71
},
{
"assembly": [
{
"encoding": [
{
"name": "19",
"offset": 0,
"size": 6
},
{
"name": "BF",
"offset": 6,
"size": 3
},
{
"name": "//",
"offset": 9,
"size": 2
},
{
"name": "BFA",
"offset": 11,
"size": 3
},
{
"name": "//",
"offset": 14,
"size": 2
},
{
"name": "///",
"offset": 16,
"size": 5
},
{
"name": "0",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Move Condition Register Field XL-form",
"texts": [
"mcrf BF,BFA"
]
}
],
"extended_mnemonics": [],
"page": 72
},
{
"assembly": [
{
"encoding": [
{
"name": "17",
"offset": 0,
"size": 6
},
{
"name": "///",
"offset": 6,
"size": 5
},
{
"name": "///",
"offset": 11,
"size": 5
},
{
"name": "///",
"offset": 16,
"size": 4
},
{
"name": "LEV",
"offset": 20,
"size": 7
},
{
"name": "///",
"offset": 27,
"size": 3
},
{
"name": "1",
"offset": 30,
"size": 1
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "System Call SC-form",
"texts": [
"sc LEV"
]
},
{
"encoding": [
{
"name": "17",
"offset": 0,
"size": 6
},
{
"name": "///",
"offset": 6,
"size": 5
},
{
"name": "///",
"offset": 11,
"size": 5
},
{
"name": "///",
"offset": 16,
"size": 4
},
{
"name": "LEV",
"offset": 20,
"size": 7
},
{
"name": "///",
"offset": 27,
"size": 3
},
{
"name": "0",
"offset": 30,
"size": 1
},
{
"name": "1",
"offset": 31,
"size": 1
}
],
"heading": "System Call Vectored SC-form",
"texts": [
"scv LEV"
]
}
],
"extended_mnemonics": [],
"page": 73
},
{
"assembly": [
{
"encoding": [
{
"name": "34",
"offset": 0,
"size": 6
},
{
"name": "RT",
"offset": 6,
"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "D",
"offset": 16,
"size": 16
}
],
"heading": "Load Byte and Zero D-form",
"texts": [
"lbz RT,D(RA)"
]
},
{
"encoding": [
{
"name": "1",
"offset": 0,
"size": 6
},
{
"name": "2",
"offset": 6,
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},
{
"name": "0",
"offset": 8,
"size": 1
},
{
"name": "//",
"offset": 9,
"size": 2
},
{
"name": "R",
"offset": 11,
"size": 1
},
{
"name": "//",
"offset": 12,
"size": 2
},
{
"name": "d0",
"offset": 14,
"size": 18
},
{
"name": "34",
"offset": 32,
"size": 6
},
{
"name": "RT",
"offset": 38,
"size": 5
},
{
"name": "RA",
"offset": 43,
"size": 5
},
{
"name": "d1",
"offset": 48,
"size": 16
}
],
"heading": "Prefixed Load Byte and Zero MLS:D-form",
"texts": [
"plbz RT,D(RA),R"
]
}
],
"extended_mnemonics": [
"plbz Rx,value(Ry) plbz Rx,value(Ry),0",
"plbz Rx,value plbz Rx,value(0),1"
],
"page": 78
},
{
"assembly": [
{
"encoding": [
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"name": "31",
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},
{
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},
{
"name": "87",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Load Byte and Zero Indexed X-form",
"texts": [
"lbzx RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 78
},
{
"assembly": [
{
"encoding": [
{
"name": "35",
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{
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"size": 5
},
{
"name": "D",
"offset": 16,
"size": 16
}
],
"heading": "Load Byte and Zero with Update D-form",
"texts": [
"lbzu RT,D(RA)"
]
}
],
"extended_mnemonics": [],
"page": 78
},
{
"assembly": [
{
"encoding": [
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{
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{
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"size": 5
},
{
"name": "RB",
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"size": 5
},
{
"name": "119",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Load Byte and Zero with Update Indexed X-form",
"texts": [
"lbzux RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 78
},
{
"assembly": [
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"encoding": [
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{
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"size": 5
},
{
"name": "D",
"offset": 16,
"size": 16
}
],
"heading": "Load Halfword and Zero D-form",
"texts": [
"lhz RT,D(RA)"
]
},
{
"encoding": [
{
"name": "1",
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"size": 6
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{
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{
"name": "0",
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"size": 1
},
{
"name": "//",
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},
{
"name": "R",
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"size": 1
},
{
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"size": 2
},
{
"name": "d0",
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{
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{
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},
{
"name": "RA",
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},
{
"name": "d1",
"offset": 48,
"size": 16
}
],
"heading": "Prefixed Load Halfword and Zero MLS:D-form",
"texts": [
"plhz RT,D(RA),R"
]
}
],
"extended_mnemonics": [
"plhz Rx,value(Ry) plhz Rx,value(Ry),0",
"plhz Rx,value plhz Rx,value(0),1"
],
"page": 79
},
{
"assembly": [
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{
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},
{
"name": "279",
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"size": 10
},
{
"name": "/",
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"size": 1
}
],
"heading": "Load Halfword and Zero Indexed X-form",
"texts": [
"lhzx RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 79
},
{
"assembly": [
{
"encoding": [
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "D",
"offset": 16,
"size": 16
}
],
"heading": "Load Halfword and Zero with Update D-form",
"texts": [
"lhzu RT,D(RA)"
]
}
],
"extended_mnemonics": [],
"page": 79
},
{
"assembly": [
{
"encoding": [
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{
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},
{
"name": "311",
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},
{
"name": "/",
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"size": 1
}
],
"heading": "Load Halfword and Zero with Update Indexed X-form",
"texts": [
"lhzux RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 79
},
{
"assembly": [
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "D",
"offset": 16,
"size": 16
}
],
"heading": "Load Halfword Algebraic D-form",
"texts": [
"lha RT,D(RA)"
]
},
{
"encoding": [
{
"name": "1",
"offset": 0,
"size": 6
},
{
"name": "2",
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{
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{
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},
{
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},
{
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},
{
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},
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"size": 6
},
{
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"size": 5
},
{
"name": "RA",
"offset": 43,
"size": 5
},
{
"name": "d1",
"offset": 48,
"size": 16
}
],
"heading": "Prefixed Load Halfword Algebraic MLS:D-form",
"texts": [
"plha RT,D(RA),R"
]
}
],
"extended_mnemonics": [
"plha Rx,value(Ry) plha Rx,value(Ry),0",
"plha Rx,value plha Rx,value(0),1"
],
"page": 80
},
{
"assembly": [
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{
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{
"name": "343",
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"size": 10
},
{
"name": "/",
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"size": 1
}
],
"heading": "Load Halfword Algebraic Indexed X-form",
"texts": [
"lhax RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 80
},
{
"assembly": [
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],
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{
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}
],
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"texts": [
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}
],
"extended_mnemonics": [
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"la Rx,disp(Ry) addi Rx,Ry,disp",
"subi Rx,Ry,value addi Rx,Ry,-value",
"paddi Rx,Ry,value paddi Rx,Ry,value,0",
"pli Rx,value paddi Rx,0,value,0",
"pla Rx,value(Ry) paddi Rx,Ry,value,0",
"pla Rx,value paddi Rx,0,value,1",
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],
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],
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{
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],
"heading": "Add PC Immediate Shifted DX-form",
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],
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{
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{
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{
"name": "Rc",
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}
],
"heading": "Add XO-form",
"texts": [
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"add. RT,RA,RB (OE=0 Rc=1)",
"addo RT,RA,RB (OE=1 Rc=0)",
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}
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],
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],
"heading": "Add Immediate Carrying and Record D-form",
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],
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"size": 1
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{
"name": "40",
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"size": 9
},
{
"name": "Rc",
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"size": 1
}
],
"heading": "Subtract From XO-form",
"texts": [
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"subf. RT,RA,RB (OE=0 Rc=1)",
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"subfo. RT,RA,RB (OE=1 Rc=1)"
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}
],
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],
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],
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"addc. RT,RA,RB (OE=0 Rc=1)",
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"adde. RT,RA,RB (OE=0 Rc=1)",
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{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "OE",
"offset": 21,
"size": 1
},
{
"name": "457",
"offset": 22,
"size": 9
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Divide Doubleword Unsigned XO-form",
"texts": [
"divdu RT,RA,RB (OE=0 Rc=0)",
"divdu. RT,RA,RB (OE=0 Rc=1)",
"divduo RT,RA,RB (OE=1 Rc=0)",
"divduo. RT,RA,RB (OE=1 Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 115
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
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{
"name": "RT",
"offset": 6,
"size": 5
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "OE",
"offset": 21,
"size": 1
},
{
"name": "425",
"offset": 22,
"size": 9
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Divide Doubleword Extended XO-form",
"texts": [
"divde RT,RA,RB (OE=0 Rc=0)",
"divde. RT,RA,RB (OE=0 Rc=1)",
"divdeo RT,RA,RB (OE=1 Rc=0)",
"divdeo. RT,RA,RB (OE=1 Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 116
},
{
"assembly": [
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"encoding": [
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{
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"size": 5
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{
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{
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{
"name": "393",
"offset": 22,
"size": 9
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Divide Doubleword Extended Unsigned XO-form",
"texts": [
"divdeu RT,RA,RB (OE=0 Rc=0)",
"divdeu. RT,RA,RB (OE=0 Rc=1)",
"divdeuo RT,RA,RB (OE=1 Rc=0)",
"divdeuo. RT,RA,RB (OE=1 Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 116
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{
"assembly": [
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"size": 5
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{
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{
"name": "777",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Modulo Signed Doubleword X-form",
"texts": [
"modsd RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 117
},
{
"assembly": [
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"encoding": [
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{
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"size": 10
},
{
"name": "/",
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"size": 1
}
],
"heading": "Modulo Unsigned Doubleword X-form",
"texts": [
"modud RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 117
},
{
"assembly": [
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{
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "SI",
"offset": 16,
"size": 16
}
],
"heading": "Compare Immediate D-form",
"texts": [
"cmpi BF,L,RA,SI"
]
}
],
"extended_mnemonics": [
"cmpdi Rx,value cmpi 0,1,Rx,value",
"cmpwi cr3,Rx,value cmpi 3,0,Rx,value"
],
"page": 119
},
{
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{
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{
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"size": 5
},
{
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"size": 5
},
{
"name": "0",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Compare X-form",
"texts": [
"cmp BF,L,RA,RB"
]
}
],
"extended_mnemonics": [
"cmpd Rx,Ry cmp 0,1,Rx,Ry",
"cmpd cr3,Rx,Ry cmp 3,0,Rx,Ry"
],
"page": 119
},
{
"assembly": [
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"size": 1
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{
"name": "L",
"offset": 10,
"size": 1
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "Compare Logical Immediate D-form",
"texts": [
"cmpli BF,L,RA,UI"
]
}
],
"extended_mnemonics": [
"cmpldi Rx,value cmpli 0,1,Rx,value",
"cmplwi cr3,Rx,value cmpli 3,0,Rx,value"
],
"page": 119
},
{
"assembly": [
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"size": 1
},
{
"name": "L",
"offset": 10,
"size": 1
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "32",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Compare Logical X-form",
"texts": [
"cmpl BF,L,RA,RB"
]
}
],
"extended_mnemonics": [
"cmpld Rx,Ry cmpl 0,1,Rx,Ry",
"cmplw cr3,Rx,Ry cmpl 3,0,Rx,Ry"
],
"page": 119
},
{
"assembly": [
{
"encoding": [
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{
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"size": 3
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{
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"offset": 9,
"size": 1
},
{
"name": "L",
"offset": 10,
"size": 1
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "192",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Compare Ranged Byte X-form",
"texts": [
"cmprb BF,L,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 120
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
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{
"name": "BF",
"offset": 6,
"size": 3
},
{
"name": "//",
"offset": 9,
"size": 2
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "224",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Compare Equal Byte X-form",
"texts": [
"cmpeqb BF,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 121
},
{
"assembly": [
{
"encoding": [
{
"name": "3",
"offset": 0,
"size": 6
},
{
"name": "TO",
"offset": 6,
"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "SI",
"offset": 16,
"size": 16
}
],
"heading": "Trap Word Immediate D-form",
"texts": [
"twi TO,RA,SI"
]
}
],
"extended_mnemonics": [
"twgti Rx,value tw 8,Rx,value",
"twllei Rx,value tw 6,Rx,value"
],
"page": 123
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
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{
"name": "TO",
"offset": 6,
"size": 5
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "4",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Trap Word X-form",
"texts": [
"tw TO,RA,RB"
]
}
],
"extended_mnemonics": [
"tweq Rx,Ry tw 4,Rx,Ry",
"twlge Rx,Ry tw 5,Rx,Ry",
"trap tw 31,0,0"
],
"page": 123
},
{
"assembly": [
{
"encoding": [
{
"name": "2",
"offset": 0,
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{
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "SI",
"offset": 16,
"size": 16
}
],
"heading": "Trap Doubleword Immediate D-form",
"texts": [
"tdi TO,RA,SI"
]
}
],
"extended_mnemonics": [
"tdlti Rx,value tdi 16,Rx,value",
"tdnei Rx,value tdi 24,Rx,value"
],
"page": 124
},
{
"assembly": [
{
"encoding": [
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{
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"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "BC",
"offset": 21,
"size": 5
},
{
"name": "15",
"offset": 26,
"size": 5
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Integer Select A-form",
"texts": [
"isel RT,RA,RB,BC"
]
}
],
"extended_mnemonics": [],
"page": 124
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
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{
"name": "TO",
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"size": 5
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "68",
"offset": 21,
"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Trap Doubleword X-form",
"texts": [
"td TO,RA,RB"
]
}
],
"extended_mnemonics": [
"tdge Rx,Ry td 12,Rx,Ry",
"tdlnl Rx,Ry td 5,Rx,Ry",
"isellt Rx,Ry,Rz isel Rx,Ry,Rz,0",
"iselgt Rx,Ry,Rz isel Rx,Ry,Rz,1",
"iseleq Rx,Ry,Rz isel Rx,Ry,Rz,2"
],
"page": 124
},
{
"assembly": [
{
"encoding": [
{
"name": "28",
"offset": 0,
"size": 6
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{
"name": "RS",
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "AND Immediate D-form",
"texts": [
"andi. RA,RS,UI"
]
}
],
"extended_mnemonics": [],
"page": 125
},
{
"assembly": [
{
"encoding": [
{
"name": "29",
"offset": 0,
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{
"name": "RS",
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "AND Immediate Shifted D-form",
"texts": [
"andis. RA,RS,UI"
]
}
],
"extended_mnemonics": [],
"page": 125
},
{
"assembly": [
{
"encoding": [
{
"name": "24",
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "OR Immediate D-form",
"texts": [
"ori RA,RS,UI"
]
}
],
"extended_mnemonics": [
"no-op ori 0,0,0"
],
"page": 125
},
{
"assembly": [
{
"encoding": [
{
"name": "25",
"offset": 0,
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{
"name": "RS",
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "OR Immediate Shifted D-form",
"texts": [
"oris RA,RS,UI"
]
}
],
"extended_mnemonics": [],
"page": 126
},
{
"assembly": [
{
"encoding": [
{
"name": "26",
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"name": "RS",
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},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "XOR Immediate D-form",
"texts": [
"xori RA,RS,UI"
]
}
],
"extended_mnemonics": [
"xnop xori 0,0,0"
],
"page": 126
},
{
"assembly": [
{
"encoding": [
{
"name": "27",
"offset": 0,
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{
"name": "RS",
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{
"name": "RA",
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"size": 5
},
{
"name": "UI",
"offset": 16,
"size": 16
}
],
"heading": "XOR Immediate Shifted D-form",
"texts": [
"xoris RA,RS,UI"
]
}
],
"extended_mnemonics": [],
"page": 126
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
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{
"name": "RS",
"offset": 6,
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "28",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "AND X-form",
"texts": [
"and RA,RS,RB (Rc=0)",
"and. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 126
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
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"name": "RS",
"offset": 6,
"size": 5
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "316",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "XOR X-form",
"texts": [
"xor RA,RS,RB (Rc=0)",
"xor. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 126
},
{
"assembly": [
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"encoding": [
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"name": "RS",
"offset": 6,
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "476",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "NAND X-form",
"texts": [
"nand RA,RS,RB (Rc=0)",
"nand. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 126
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
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{
"name": "RS",
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"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "444",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "OR X-form",
"texts": [
"or RA,RS,RB (Rc=0)",
"or. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [
"mr Rx,Ry or Rx,Ry,Ry"
],
"page": 127
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
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{
"name": "RS",
"offset": 6,
"size": 5
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{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "412",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "OR with Complement X-form",
"texts": [
"orc RA,RS,RB (Rc=0)",
"orc. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 127
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
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{
"name": "RS",
"offset": 6,
"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "124",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "NOR X-form",
"texts": [
"nor RA,RS,RB (Rc=0)",
"nor. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [
"not Rx,Ry nor Rx,Ry,Ry"
],
"page": 127
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
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{
"name": "RS",
"offset": 6,
"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "284",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Equivalent X-form",
"texts": [
"eqv RA,RS,RB (Rc=0)",
"eqv. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 127
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
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{
"name": "RS",
"offset": 6,
"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "60",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "AND with Complement X-form",
"texts": [
"andc RA,RS,RB (Rc=0)",
"andc. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 127
},
{
"assembly": [
{
"encoding": [
{
"name": "31",
"offset": 0,
"size": 6
},
{
"name": "RS",
"offset": 6,
"size": 5
},
{
"name": "RA",
"offset": 11,
"size": 5
},
{
"name": "///",
"offset": 16,
"size": 5
},
{
"name": "954",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Extend Sign Byte X-form",
"texts": [
"extsb RA,RS (Rc=0)",
"extsb. RA,RS (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 128
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{
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],
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]
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],
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]
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],
"heading": "Count Leading Zeros Doubleword under bit Mask X-form",
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]
}
],
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],
"heading": "Bit Permute Doubleword X-form",
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]
}
],
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{
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],
"heading": "Centrifuge Doubleword X-form",
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]
}
],
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},
{
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"heading": "Parallel Bits Extract Doubleword X-form",
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]
}
],
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{
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"heading": "Parallel Bits Deposit Doubleword X-form",
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]
}
],
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{
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}
],
"heading": "Rotate Left Word Immediate then AND with Mask M-form",
"texts": [
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"rlwinm. RA,RS,SH,MB,ME (Rc=1)"
]
}
],
"extended_mnemonics": [
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"srwi Rx,Ry,n rlwinm Rx,Ry,32-n,n,31",
"clrrwi Rx,Ry,n rlwinm Rx,Ry,0,0,31-n"
],
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],
"heading": "Rotate Left Word then AND with Mask M-form",
"texts": [
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"rlwnm. RA,RS,RB,MB,ME (Rc=1)"
]
}
],
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{
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}
],
"heading": "Rotate Left Word Immediate then Mask Insert M-form",
"texts": [
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"rlwimi. RA,RS,SH,MB,ME (Rc=1)"
]
}
],
"extended_mnemonics": [
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{
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}
],
"heading": "Rotate Left Doubleword Immediate then Clear Left MD-form",
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"rldicl. RA,RS,SH,MB (Rc=1)"
]
}
],
"extended_mnemonics": [
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],
"heading": "Rotate Left Doubleword Immediate then Clear Right MD-form",
"texts": [
"rldicr RA,RS,SH,ME (Rc=0)",
"rldicr. RA,RS,SH,ME (Rc=1)"
]
}
],
"extended_mnemonics": [
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"sldi Rx,Ry,n rldicr Rx,Ry,n,63-n",
"clrrdi Rx,Ry,n rldicr Rx,Ry,0,63-n"
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],
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"rldic. RA,RS,SH,MB (Rc=1)"
]
}
],
"extended_mnemonics": [
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{
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}
],
"heading": "Rotate Left Doubleword then Clear Left MDS-form",
"texts": [
"rldcl RA,RS,RB,MB (Rc=0)",
"rldcl. RA,RS,RB,MB (Rc=1)"
]
}
],
"extended_mnemonics": [
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],
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{
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{
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}
],
"heading": "Rotate Left Doubleword then Clear Right MDS-form",
"texts": [
"rldcr RA,RS,RB,ME (Rc=0)",
"rldcr. RA,RS,RB,ME (Rc=1)"
]
}
],
"extended_mnemonics": [],
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},
{
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},
{
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"size": 1
}
],
"heading": "Rotate Left Doubleword Immediate then Mask Insert MD-form",
"texts": [
"rldimi RA,RS,SH,MB (Rc=0)",
"rldimi. RA,RS,SH,MB (Rc=1)"
]
}
],
"extended_mnemonics": [
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{
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{
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{
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},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Shift Left Word X-form",
"texts": [
"slw RA,RS,RB (Rc=0)",
"slw. RA,RS,RB (Rc=1)"
]
}
],
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{
"name": "RB",
"offset": 16,
"size": 5
},
{
"name": "536",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Shift Right Word X-form",
"texts": [
"srw RA,RS,RB (Rc=0)",
"srw. RA,RS,RB (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 139
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],
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],
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],
"heading": "Extend Sign Word and Shift Left Immediate XS-form",
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}
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"extended_mnemonics": [],
"page": 142
},
{
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"size": 1
}
],
"heading": "Convert Declets To Binary Coded Decimal X-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 143
},
{
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}
],
"heading": "Convert Binary Coded Decimal To Declets X-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 143
},
{
"assembly": [
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"size": 9
},
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}
],
"heading": "Add and Generate Sixes XO-form",
"texts": [
"addg6s RT,RA,RB"
]
}
],
"extended_mnemonics": [],
"page": 144
},
{
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}
],
"heading": "Byte-Reverse Halfword X-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 145
},
{
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],
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"texts": [
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}
],
"extended_mnemonics": [],
"page": 145
},
{
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],
"heading": "Byte-Reverse Doubleword X-form",
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}
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"page": 145
},
{
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{
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"offset": 31,
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}
],
"heading": "Hash Store X-form",
"texts": [
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}
],
"extended_mnemonics": [],
"page": 147
},
{
"assembly": [
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"size": 10
},
{
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"size": 1
}
],
"heading": "Hash Check X-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 147
},
{
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{
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}
],
"heading": "Move From VSR Doubleword X-form",
"texts": [
"mfvsrd RA,XS"
]
}
],
"extended_mnemonics": [
"mffprd RA,FRS mfvsrd RA,FRS",
"mfvrd RA,VRS mfvsrd RA,VRS+32"
],
"page": 149
},
{
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},
{
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"offset": 31,
"size": 1
}
],
"heading": "Move From VSR Lower Doubleword X-form",
"texts": [
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}
],
"extended_mnemonics": [],
"page": 149
},
{
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},
{
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"offset": 31,
"size": 1
}
],
"heading": "Move From VSR Word and Zero X-form",
"texts": [
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]
}
],
"extended_mnemonics": [
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"page": 150
},
{
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"size": 10
},
{
"name": "TX",
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"size": 1
}
],
"heading": "Move To VSR Doubleword X-form",
"texts": [
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]
}
],
"extended_mnemonics": [
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"mtvrd VRT,RA mtvsrd VRT+32,RA"
],
"page": 150
},
{
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{
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"size": 10
},
{
"name": "TX",
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"size": 1
}
],
"heading": "Move To VSR Word Algebraic X-form",
"texts": [
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]
}
],
"extended_mnemonics": [
"mtfprwa FRT,RA mtvsrwa FRT,RA",
"mtvrwa VRT,RA mtvsrwa VRT+32,RA"
],
"page": 151
},
{
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{
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"size": 10
},
{
"name": "TX",
"offset": 31,
"size": 1
}
],
"heading": "Move To VSR Word and Zero X-form",
"texts": [
"mtvsrwz XT,RA"
]
}
],
"extended_mnemonics": [
"mtfprwz FRT,RA mtvsrwz FRT,RA",
"mtvrwz VRT,RA mtvsrwz VRT+32,RA"
],
"page": 151
},
{
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{
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"size": 10
},
{
"name": "TX",
"offset": 31,
"size": 1
}
],
"heading": "Move To VSR Double Doubleword X-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 152
},
{
"assembly": [
{
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{
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"size": 10
},
{
"name": "TX",
"offset": 31,
"size": 1
}
],
"heading": "Move To VSR Word & Splat X-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 152
},
{
"assembly": [
{
"encoding": [
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{
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"size": 10
},
{
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"offset": 31,
"size": 1
}
],
"heading": "Move To Special Purpose Register XFX-form",
"texts": [
"mtspr SPR,RS"
]
}
],
"extended_mnemonics": [
"mtxer Rx mtspr 1,Rx",
"mtlr Rx mtspr 8,Rx",
"mtctr Rx mtspr 9,Rx",
"mtppr Rx mtspr 896,Rx",
"mtppr32 Rx mtspr 898,Rx"
],
"page": 153
},
{
"assembly": [
{
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"size": 6
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{
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{
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"size": 10
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{
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"size": 10
},
{
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"offset": 31,
"size": 1
}
],
"heading": "Move From Special Purpose Register XFX-form",
"texts": [
"mfspr RT,SPR"
]
}
],
"extended_mnemonics": [
"mfxer Rx mfspr Rx,1",
"mflr Rx mfspr Rx,8",
"mfctr Rx mfspr Rx,9"
],
"page": 155
},
{
"assembly": [
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"size": 6
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{
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{
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{
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"size": 1
}
],
"heading": "Move to CR from XER Extended X-form",
"texts": [
"mcrxrx BF"
]
}
],
"extended_mnemonics": [],
"page": 156
},
{
"assembly": [
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"size": 8
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"size": 1
},
{
"name": "144",
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"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Move To One Condition Register Field XFX-form",
"texts": [
"mtocrf FXM,RS"
]
}
],
"extended_mnemonics": [],
"page": 156
},
{
"assembly": [
{
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{
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"size": 1
},
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"size": 1
},
{
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"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Move To Condition Register Fields XFX-form",
"texts": [
"mtcrf FXM,RS"
]
}
],
"extended_mnemonics": [
"mtcr Rx mtcrf 0xFF,Rx"
],
"page": 156
},
{
"assembly": [
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"size": 1
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{
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{
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"size": 10
},
{
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"offset": 31,
"size": 1
}
],
"heading": "Move From One Condition Register Field XFX-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 157
},
{
"assembly": [
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{
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"size": 1
}
],
"heading": "Move From Condition Register XFX-form",
"texts": [
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]
}
],
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],
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"size": 10
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "Move From FPSCR Lightweight X-form",
"texts": [
"mffsl FRT"
]
}
],
"extended_mnemonics": [],
"page": 213
},
{
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{
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"size": 10
},
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"offset": 31,
"size": 1
}
],
"heading": "Move to Condition Register from FPSCR X-form",
"texts": [
"mcrfs BF,BFA"
]
}
],
"extended_mnemonics": [],
"page": 214
},
{
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},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "Move To FPSCR Field Immediate X-form",
"texts": [
"mtfsfi BF,U,W (Rc=0)",
"mtfsfi. BF,U,W (Rc=1)"
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],
"extended_mnemonics": [],
"page": 214
},
{
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"size": 1
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{
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"offset": 7,
"size": 8
},
{
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"size": 1
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{
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},
{
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],
"heading": "Move To FPSCR Fields XFL-form",
"texts": [
"mtfsf FLM,FRB,L,W (Rc=0)",
"mtfsf. FLM,FRB,L,W (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 214
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},
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"offset": 31,
"size": 1
}
],
"heading": "Move To FPSCR Bit 0 X-form",
"texts": [
"mtfsb0 BT (Rc=0)",
"mtfsb0. BT (Rc=1)"
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}
],
"extended_mnemonics": [],
"page": 215
},
{
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"offset": 31,
"size": 1
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],
"heading": "Move To FPSCR Bit 1 X-form",
"texts": [
"mtfsb1 BT (Rc=0)",
"mtfsb1. BT (Rc=1)"
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}
],
"extended_mnemonics": [],
"page": 215
},
{
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"offset": 6,
"size": 5
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{
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"offset": 11,
"size": 5
},
{
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"offset": 16,
"size": 5
},
{
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"offset": 21,
"size": 10
},
{
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"offset": 31,
"size": 1
}
],
"heading": "DFP Add X-form",
"texts": [
"dadd FRT,FRA,FRB (Rc=0)",
"dadd. FRT,FRA,FRB (Rc=1)"
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},
{
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"offset": 0,
"size": 6
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{
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"offset": 6,
"size": 5
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{
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"offset": 11,
"size": 5
},
{
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"offset": 16,
"size": 5
},
{
"name": "2",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Add Quad X-form",
"texts": [
"daddq FRTp,FRAp,FRBp (Rc=0)",
"daddq. FRTp,FRAp,FRBp (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 236
},
{
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"offset": 11,
"size": 5
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{
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"offset": 16,
"size": 5
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{
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"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Subtract X-form",
"texts": [
"dsub FRT,FRA,FRB (Rc=0)",
"dsub. FRT,FRA,FRB (Rc=1)"
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},
{
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"size": 6
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{
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"offset": 6,
"size": 5
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{
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"offset": 11,
"size": 5
},
{
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"offset": 16,
"size": 5
},
{
"name": "514",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Subtract Quad X-form",
"texts": [
"dsubq FRTp,FRAp,FRBp (Rc=0)",
"dsubq. FRTp,FRAp,FRBp (Rc=1)"
]
}
],
"extended_mnemonics": [],
"page": 236
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"offset": 11,
"size": 5
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{
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"offset": 16,
"size": 5
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"size": 10
},
{
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"offset": 31,
"size": 1
}
],
"heading": "DFP Multiply X-form",
"texts": [
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"dmul. FRT,FRA,FRB (Rc=1)"
]
},
{
"encoding": [
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"offset": 0,
"size": 6
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{
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"offset": 6,
"size": 5
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{
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"offset": 11,
"size": 5
},
{
"name": "FRBp",
"offset": 16,
"size": 5
},
{
"name": "34",
"offset": 21,
"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Multiply Quad X-form",
"texts": [
"dmulq FRTp,FRAp,FRBp (Rc=0)",
"dmulq. FRTp,FRAp,FRBp (Rc=1)"
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}
],
"extended_mnemonics": [],
"page": 238
},
{
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{
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"offset": 11,
"size": 5
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{
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"offset": 16,
"size": 5
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{
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"size": 10
},
{
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"offset": 31,
"size": 1
}
],
"heading": "DFP Divide X-form",
"texts": [
"ddiv FRT,FRA,FRB (Rc=0)",
"ddiv. FRT,FRA,FRB (Rc=1)"
]
},
{
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"offset": 0,
"size": 6
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{
"name": "FRTp",
"offset": 6,
"size": 5
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{
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"offset": 11,
"size": 5
},
{
"name": "FRBp",
"offset": 16,
"size": 5
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{
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"size": 10
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Divide Quad X-form",
"texts": [
"ddivq FRTp,FRAp,FRBp (Rc=0)",
"ddivq. FRTp,FRAp,FRBp (Rc=1)"
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}
],
"extended_mnemonics": [],
"page": 239
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"size": 10
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"size": 1
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],
"heading": "DFP Compare Unordered X-form",
"texts": [
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},
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"size": 5
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"size": 10
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"offset": 31,
"size": 1
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],
"heading": "DFP Compare Unordered Quad X-form",
"texts": [
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"heading": "DFP Compare Ordered X-form",
"texts": [
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"size": 5
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"size": 10
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"name": "/",
"offset": 31,
"size": 1
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],
"heading": "DFP Compare Ordered Quad X-form",
"texts": [
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},
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"size": 2
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"size": 5
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{
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"offset": 16,
"size": 6
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"size": 9
},
{
"name": "/",
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"size": 1
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],
"heading": "DFP Test Data Class Z22-form",
"texts": [
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},
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"size": 2
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"offset": 11,
"size": 5
},
{
"name": "DCM",
"offset": 16,
"size": 6
},
{
"name": "194",
"offset": 22,
"size": 9
},
{
"name": "/",
"offset": 31,
"size": 1
}
],
"heading": "DFP Test Data Class Quad Z22-form",
"texts": [
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]
}
],
"extended_mnemonics": [],
"page": 243
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{
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"size": 2
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{
"name": "FRA",
"offset": 11,
"size": 5
},
{
"name": "DGM",
"offset": 16,
"size": 6
},
{
"name": "226",
"offset": 22,
"size": 9
},
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"offset": 31,
"size": 1
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],
"heading": "DFP Test Data Group Z22-form",
"texts": [
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},
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"size": 5
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"offset": 16,
"size": 6
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"size": 9
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"size": 1
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"heading": "DFP Test Data Group Quad Z22-form",
"texts": [
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]
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"size": 5
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"size": 10
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"size": 1
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],
"heading": "DFP Test Exponent X-form",
"texts": [
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},
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"offset": 16,
"size": 5
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"size": 10
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"offset": 31,
"size": 1
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],
"heading": "DFP Test Exponent Quad X-form",
"texts": [
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]
}
],
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"size": 1
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],
"heading": "DFP Test Significance X-form",
"texts": [
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},
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"size": 10
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"size": 1
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],
"heading": "DFP Test Significance Quad X-form",
"texts": [
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{
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"size": 1
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{
"name": "UIM",
"offset": 10,
"size": 6
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{
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"size": 5
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"size": 10
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],
"heading": "DFP Test Significance Immediate X-form",
"texts": [
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"size": 1
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{
"name": "UIM",
"offset": 10,
"size": 6
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"size": 5
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"size": 1
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"heading": "DFP Test Significance Immediate Quad X-form",
"texts": [
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{
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{
"name": "FRT",
"offset": 6,
"size": 5
},
{
"name": "TE",
"offset": 11,
"size": 5
},
{
"name": "FRB",
"offset": 16,
"size": 5
},
{
"name": "RMC",
"offset": 21,
"size": 2
},
{
"name": "67",
"offset": 23,
"size": 8
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Quantize Immediate Z23-form",
"texts": [
"dquai TE,FRT,FRB,RMC (Rc=0)",
"dquai. TE,FRT,FRB,RMC (Rc=1)"
]
},
{
"encoding": [
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"name": "63",
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"size": 6
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{
"name": "FRTp",
"offset": 6,
"size": 5
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{
"name": "TE",
"offset": 11,
"size": 5
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{
"name": "FRBp",
"offset": 16,
"size": 5
},
{
"name": "RMC",
"offset": 21,
"size": 2
},
{
"name": "67",
"offset": 23,
"size": 8
},
{
"name": "Rc",
"offset": 31,
"size": 1
}
],
"heading": "DFP Quantize Immediate Quad Z23-form",
"texts": [
"dquaiq TE,FRTp,FRBp,RMC (Rc=0)",
"dquaiq. TE,FRTp,FRBp,RMC (Rc=1)"
]
}
],
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{
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{
"name": "FRA",
"offset": 11,
"size": 5
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{
"name": "FRB",
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"size": 5
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"offset": 21,
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],
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"dqua. FRT,FRA,FRB,RMC (Rc=1)"
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"texts": [
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"dquaq. FRTp,FRAp,FRBp,RMC (Rc=1)"
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"heading": "DFP Reround Quad Z23-form",
"texts": [
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"heading": "DFP Round To FP Integer Without Inexact Quad Z23-form",
"texts": [
"drintnq R,FRTp,FRBp,RMC (Rc=0)",
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"texts": [
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"dctdp. FRT,FRB (Rc=1)"
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],
"heading": "DFP Convert To DFP Extended X-form",
"texts": [
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"dctqpq. FRTp,FRB (Rc=1)"
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],
"heading": "DFP Round To DFP Short X-form",
"texts": [
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],
"heading": "DFP Round To DFP Long X-form",
"texts": [
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"texts": [
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],
"heading": "DFP Convert To Fixed Quad X-form",
"texts": [
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"dctfixq. FRT,FRBp (Rc=1)"
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}
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"heading": "DFP Convert To Fixed Quadword Quad X-form",
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}
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],
"heading": "DFP Decode DPD To BCD X-form",
"texts": [
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},
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},
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"size": 1
}
],
"heading": "DFP Decode DPD To BCD Quad X-form",
"texts": [
"ddedpdq SP,FRTp,FRBp (Rc=0)",
"ddedpdq. SP,FRTp,FRBp (Rc=1)"
]
}
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],
"heading": "DFP Encode BCD To DPD X-form",
"texts": [
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},
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"size": 1
}
],
"heading": "DFP Encode BCD To DPD Quad X-form",
"texts": [
"denbcdq S,FRTp,FRBp (Rc=0)",
"denbcdq. S,FRTp,FRBp (Rc=1)"
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}
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],
"heading": "DFP Extract Biased Exponent X-form",
"texts": [
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"dxex. FRT,FRB (Rc=1)"
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},
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"size": 1
}
],
"heading": "DFP Extract Biased Exponent Quad X-form",
"texts": [
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"dxexq. FRT,FRBp (Rc=1)"
]
}
],
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}
],
"heading": "DFP Insert Biased Exponent X-form",
"texts": [
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"diex. FRT,FRA,FRB (Rc=1)"
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},
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"size": 1
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],
"heading": "DFP Insert Biased Exponent Quad X-form",
"texts": [
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"diexq. FRTp,FRA,FRBp (Rc=1)"
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],
"heading": "DFP Shift Significand Left Immediate Z22-form",
"texts": [
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"dscli. FRT,FRA,SH (Rc=1)"
]
},
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}
],
"heading": "DFP Shift Significand Left Immediate Quad Z22-form",
"texts": [
"dscliq FRTp,FRAp,SH (Rc=0)",
"dscliq. FRTp,FRAp,SH (Rc=1)"
]
}
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],
"heading": "DFP Shift Significand Right Immediate Z22-form",
"texts": [
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"dscri. FRT,FRA,SH (Rc=1)"
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},
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}
],
"extended_mnemonics": [],
"page": 1377
}
]
}
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BenjaminGrayNp1 commented Apr 12, 2023

Lots of branch instructions missing (e.g., blr)

The extended NOPs are missing (e.g., miso)

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BenjaminGrayNp1 commented Apr 12, 2023

RA.RB typo in source should be corrected in the JSON

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