SDF Delay Annotation

SDF (Standard Delay Format) is a text format for storing time delays across elements of a (digital) circuit. The collection of these delays then represents the timing of the circuit. SDF is primarily an interchange format to communicate circuit timing among EDA tools, with STA tools being the typical producers and (digital) simulators being the typical consumers.

SDF syntax and semantics follows the same principles as the other formats for modeling delay aspects of (digital) IP cells (incl. standard gates). That is, like Liberty timing models and Verilog gate/cell models, SDF represents the delays at the cell level, either as wire delays between cells or as (propagation) delays from cell inputs to cell outputs.

From the many elements that SDF can describe, these are the key ones:

• Wire delays with the INTERCONNECT construct.
• Propagation delays with the IOPATH construct.
• (Cell) timing constraints with variety of constructs, SETUPHOLD, RECREM, WIDTH, etc.

TODO: ... SDF consistency with design data ... SDF consistency with

IEEE Std 1800-2012:

SDF files contain timing values for specify path delays, specparam values, timing check constraints, and interconnect delays.

SDF Syntax

Example from SDF 3.0 std.:

(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "BIGCHIP")
(DATE "March 12, 1995 09:46")
(VENDOR "Southwestern ASIC")
(PROGRAM "Fast program")
(VERSION "1.2a")
(DIVIDER /)
(VOLTAGE 5.5:5.0:4.5)
(PROCESS "best:nom:worst")
(TEMPERATURE -40:25:125)
(TIMESCALE 100 ps)
(CELL
 (CELLTYPE "BIGCHIP")
 (INSTANCE top)
 (DELAY
  (ABSOLUTE
   (INTERCONNECT mck b/c/clk (.6:.7:.9))
   (INTERCONNECT d[0] b/c/d (.4:.5:.6))
  )
 )
)
(CELL
 (CELLTYPE "AND2")
 (INSTANCE top/b/d)
 (DELAY
  (ABSOLUTE
   (IOPATH a y (1.5:2.5:3.4) (2.5:3.6:4.7))
   (IOPATH b y (1.4:2.3:3.2) (2.3:3.4:4.3))
  )
 )
)
(CELL
 (CELLTYPE "DFF")
 (INSTANCE top/b/c)
 (DELAY
  (ABSOLUTE
   (IOPATH (posedge clk) q (2:3:4) (5:6:7))
   (PORT clr (2:3:4) (5:6:7))
  )
 )
 (TIMINGCHECK
  (SETUPHOLD d (posedge clk) (3:4:5) (-1:-1:-1))
  (WIDTH clk (4.4:7.5:11.3))
 )
)
)

Annotating from within Sim

Using $sdf_annotate(<file_path>, <inst_path>, , , "<delay_type>");, where <delay_type> is one of maximum, minimum and typical.

Questa example:

( mkdir -p questa && cd questa && \
  (test -d work || vlib work) && \
  vlog -work work ../myip.v ../stdlib.v && \
  vlog -work work ../top.v && \
  vlog -work work -sv ../tb.sv && \
  vsim -voptargs=+acc \
    -L work work.tb \
    +SDF_PATH=../top.sdf \
    -do "run -all; quit;" \
    -c \
)

Annotating through Simulator Options

Questa example:

( mkdir -p questa && cd questa && \
  (test -d work || vlib work) && \
  vlog -work work ../myip.v ../stdlib.v && \
  vlog -work work ../top.v && \
  vlog -work work -sv ../tb.sv && \
  vsim -voptargs=+acc \
    -L work work.tb \
    -sdfmax dut=../top.sdf \
    +sdf_verbose \
    -sdfannotatepercentage \
    -do "run -all; quit;" \
    -c \
)

Exporting SDF from STA Tool

PrimeTime script example:

set link_path [list myip.lib stdlib.lib]
read_verilog top.v
link

if {[file exists constraints.sdc]} {
    source constraints.sdc
}

write_sdf \
   -context verilog \
   -no_edge \
   -version 3.0 \
   -exclude {checkpins} \
   -include { SETUPHOLD RECREM } \
   "[get_object_name [current_design]].export.sdf"

Correlation between Model Elements

pin(Y) {
  timing () {                                                                              specify
    related_pin: "A" ;                                                                       specparam tdlh = 1.3;
    cell_fall(scalar) { values("1.7"); }             ((IOPATH A Y (1.3)(1.7))                specparam tdhl = 1.7;
    cell_rise(scalar) { values("1.3"); }                                                     (A => Y) = (tdlh, tdhl);
  }                                                                                        endspecify


pin(Y) {
  timing () {
    related_pin: "A" ;
    when: "B & !C";                                                                        specify
    sdf_cond: "B==1'b1 && C==1'b0";                                                          specparam tdlh = 1.3;
    cell_fall(scalar) { values("1.7"); }             (COND (B==1'b1 && C==1'b0               specparam tdhl = 1.7;
    cell_rise(scalar) { values("1.3"); }                  ((IOPATH A Y (1.3)(1.7))           if (B==1'b1 && C==1'b0) (A => Y) = (tdlh, tdhl);
  }                                                   )                                    endspecify


pin(D) {
  direction: input;
  capacitance: 0.001;                                                                      reg ntfr;
        timing() {                                                                         specify
    related_pin: "CK";                               (SETUPHOLD (posedge D)                  specparam tsr = 0.3;
    timing_type: hold_rising;                          (posedge CK) (0.3) (0.7)              specparam thr = 0.7;
    rise_constraint(scalar) { values("0.3"); }       )                                       specparam tsf = 0.2;
    fall_constraint(scalar) { values("0.2"); }       (SETUPHOLD (negedge D)                  specparam thf = 0.8;
  }                                                    (posedge CK) (0.2) (0.8)              $setuphold (posedge CK, posedge D, tsr, thr, ntfr);
  timing() {                                         )                                       $setuphold (posedge CK, negedge D, tsf, thf, ntfr);
    related_pin: "CK";                                                                     endspecify
    timing_type: setup_rising;
    rise_constraint(scalar) { values("0.7"); }
    fall_constraint(scalar) { values("0.8"); }
  }
}

Observations

• Single SDF is typically bound to a specific PVT and RC combination.
• Multiple SDF files can be annotated to the same design element/module.
• SDF may act as an input to STA tools for its delays being annotated to timing arcs.

References

https://web.archive.org/web/20190215003139/https://www2.ece.ohio-state.edu/~bibyk/ee683/BolinM_part2_timing.pdf