coldcue/7seg_shr.v

Created September 28, 2014 17:46

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coldcue created this gist Sep 28, 2014.

7seg_shr.v

-Original file line number
+Diff line change
@@ -0,0 +1,18 @@
+    module shr_4(
+        input clk,
+        input ce,
+        input rst,
+        output [3:0] out
+        );
+    reg [3:0] shr;
+    assign out = shr;
+    always @ (posedge clk)
+    	if(rst)
+    		shr <= 4'b1110;
+    	else if(ce)
+    		shr <= {shr[2:0],shr[3]};
+    endmodule