djg · August 21, 2021 06:00 · Aug 21, 2021
diff --git a/conway.sv b/conway.sv
@@ -0,0 +1,85 @@
+module top_module(
+    input clk,
+    input load,
+    input [255:0] data,
+    output [255:0] q); 
+
+    function bit[3:0] inc(input int x);
+        return x + 1;
+    endfunction
+
+    function bit[3:0] dec(input int x);
+        return x - 1;
+    endfunction
+
+    wire [15:0] row[16];
+    always @(*)
+        for (int r = 0; r < 16; r++)
+            row[r] = (load) ? data[16*r+:16] : q[16*r+:16];
+
+    genvar r;
+    generate
+        for (r = 0; r < 16; r=r+1) begin : gen
+            conway16 inst(clk, load, row[inc(r)], row[r], row[dec(r)], q[(16*r)+:16]);
+        end
+    endgenerate
+endmodule
+
+module conway16(
+    input clk,
+    input load,
+    input [15:0] U,
+    input [15:0] C,
+    input [15:0] D,
+    output [15:0] q);
+
+    function bit[3:0] inc(input int x);
+        return x + 1;
+    endfunction
+
+    function bit[3:0] dec(input int x);
+        return x - 1;
+    endfunction
+
+    //  17  16 | 31
+    //   1   0 | 15
+    // --------+
+    // 241 240  255
+    genvar c;
+    generate
+        for (c = 0; c < 16; c = c+1) begin : gen
+            conway1 inst(clk, load,
+                         U[inc(c)], U[c], U[dec(c)],
+                         C[inc(c)], C[c], C[dec(c)],
+                         D[inc(c)], D[c], D[dec(c)],
+                         q[c]);
+        end
+    endgenerate
+endmodule
+
+module conway1(
+    input clk,
+    input load,
+    input UL, U, UR,
+    input CL, C, CR,
+    input DL, D, DR,
+    output reg q);
+
+    wire q_next;
+    wire [2:0] sum;
+
+    assign sum = UL + U + UR + CL + CR + DL + D + DR;
+    always @(*)
+        case (sum)
+            3'd2: q_next <= C;
+            3'd3: q_next = 1'b1;
+            default:
+                  q_next = 1'b0;
+        endcase
+
+    always @(posedge clk)
+        if (load)
+            q <= C;
+        else
+            q <= q_next;
+endmodule
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