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  1. jcs revised this gist Jun 23, 2016. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -180,5 +180,5 @@ Remove the test clip, reattach the battery, plug the power cable in, and it shou
    ####References
    - https://lists.nongnu.org/archive/html/libreboot-dev/2015-08/msg00001.html
    - http://www.tnhh.net/2014/08/25/unbricking-chromebook-with-beaglebone.html
    - http://www.tnhh.net/mobile/posts/unbricking-chromebook-with-beaglebone.html
    - http://selinuxproject.org/~jmorris/lss2013_slides/safford_chromebook_takeown.pdf
  2. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -88,7 +88,7 @@ TODO
    #####Preparing the new image to write
    Only the first megabyte of your new coreboot ROM will be used, so you need to copy the other ~3 megs from the backup.
    Only the first megabyte of your new coreboot ROM will be used, so you need to copy the other 3 megs from the backup.
    From your build machine:
  3. jcs revised this gist Sep 4, 2015. 1 changed file with 6 additions and 2 deletions.
    8 changes: 6 additions & 2 deletions asus c201.md
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    @@ -102,10 +102,14 @@ You can verify with `fmap_decode` that your new ROM still looks like the old one
    Now `scp` it to your Chromebook and flash it:
    ````
    # flashrom final.rom
    # flashrom -w final.rom
    flashrom v0.9.4 : e6a7ca8 : May 12 2015 18:14:00 UTC on Linux 3.14.0 (armv7l), built with libpci 3.1.10, GCC 4.9.x-google 20150123 (prerelease), little endian
    Erasing and writing flash chip... Verifying flash... VERIFIED.
    SUCCESS
    ````
    Reboot and hope it works.
    Reboot and hope it worked.
    If not, continue reading.
    ####Unbricking
  4. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 9 deletions.
    10 changes: 1 addition & 9 deletions asus c201.md
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    @@ -102,15 +102,7 @@ You can verify with `fmap_decode` that your new ROM still looks like the old one
    Now `scp` it to your Chromebook and flash it:
    ````
    ~/chros/coreboot$ sudo ../flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=8M -w final.rom
    flashrom v0.9.8-r1896 on Linux 3.19.0-25-generic (x86_64)
    flashrom is free software, get the source code at http://www.flashrom.org
    Calibrating delay loop... OK.
    Found GigaDevice flash chip "GD25Q32(B)" (4096 kB, SPI) on buspirate_spi.
    Reading old flash chip contents... done.
    Erasing and writing flash chip... Erase/write done.
    Verifying flash... VERIFIED.
    # flashrom final.rom
    ````
    Reboot and hope it works.
  5. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 0 deletions.
    1 change: 1 addition & 0 deletions asus c201.md
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    @@ -173,6 +173,7 @@ No operations were specified.
    ````
    Now just flash the backup you made before reflashing, using the command above with `asus_c201_factory_flash.rom`.
    If you lost your backup, you can download the backup I made, but no guarantees that it will work on your machine:
    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - MD5 `e4478311e77745a1aff0a1117cc65010`
  6. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 4 deletions.
    5 changes: 1 addition & 4 deletions asus c201.md
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    @@ -172,10 +172,7 @@ Found GigaDevice flash chip "GD25Q32(B)" (4096 kB, SPI) on buspirate_spi.
    No operations were specified.
    ````
    Now just flash the backup you made before reflashing.
    `sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w asus_c201_factory_flash.rom`
    Now just flash the backup you made before reflashing, using the command above with `asus_c201_factory_flash.rom`.
    If you lost your backup, you can download the backup I made, but no guarantees that it will work on your machine:
    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - MD5 `e4478311e77745a1aff0a1117cc65010`
  7. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -102,7 +102,7 @@ You can verify with `fmap_decode` that your new ROM still looks like the old one
    Now `scp` it to your Chromebook and flash it:
    ````
    ~/chros/flashrom$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=8M -w ../coreboot/final.rom
    ~/chros/coreboot$ sudo ../flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=8M -w final.rom
    flashrom v0.9.8-r1896 on Linux 3.19.0-25-generic (x86_64)
    flashrom is free software, get the source code at http://www.flashrom.org
  8. jcs revised this gist Sep 4, 2015. 1 changed file with 9 additions and 1 deletion.
    10 changes: 9 additions & 1 deletion asus c201.md
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    @@ -102,7 +102,15 @@ You can verify with `fmap_decode` that your new ROM still looks like the old one
    Now `scp` it to your Chromebook and flash it:
    ````
    # flashrom -w final.rom
    ~/chros/flashrom$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=8M -w ../coreboot/final.rom
    flashrom v0.9.8-r1896 on Linux 3.19.0-25-generic (x86_64)
    flashrom is free software, get the source code at http://www.flashrom.org
    Calibrating delay loop... OK.
    Found GigaDevice flash chip "GD25Q32(B)" (4096 kB, SPI) on buspirate_spi.
    Reading old flash chip contents... done.
    Erasing and writing flash chip... Erase/write done.
    Verifying flash... VERIFIED.
    ````
    Reboot and hope it works.
  9. jcs revised this gist Sep 4, 2015. 1 changed file with 2 additions and 2 deletions.
    4 changes: 2 additions & 2 deletions asus c201.md
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    @@ -112,8 +112,8 @@ Reboot and hope it works.
    If your flashing went bad, you'll be unable to boot.
    To fix this, you'll have to reflash your backup from another machine.
    You can do this fairly easily with a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    a [SOIC8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.
    an [SOIC8 test clip](http://www.amazon.com/Pomona-5250-SOIC-Adapter-8-Pin/dp/B00SDTJBNM),
    and some cables to connect pins between the two.
    Use the instructions above to remove the keyboard.
    Remove the 8 or so screws holding the large heatsink to the case over the motherboard, exposing the battery connector.
  10. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -112,7 +112,7 @@ Reboot and hope it works.
    If your flashing went bad, you'll be unable to boot.
    To fix this, you'll have to reflash your backup from another machine.
    You can do this fairly easily with a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    a [SOIC8/SOP8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    a [SOIC8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.
    Use the instructions above to remove the keyboard.
  11. jcs revised this gist Sep 4, 2015. 1 changed file with 5 additions and 4 deletions.
    9 changes: 5 additions & 4 deletions asus c201.md
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    @@ -125,7 +125,8 @@ Attach your test clip to the flash chip located just to the left of the write-pr
    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)
    Connect pins from Bus Pirate to test clip. The SPI chip pins are as follows, with the dot in the lower left.
    Connect wires from pins of the Bus Pirate to the pins on the test clip.
    The SPI chip pins are as follows, with the dot in the lower left.
    VCC
      | HOLD
    @@ -150,11 +151,11 @@ Connect pins from Bus Pirate to test clip. The SPI chip pins are as follows, wi
    If your build machine doesn't have it already, install flashrom (`apt-get install flashrom` on Ubuntu).
    Once wired up, run `flashrom -p buspirate_spi:dev=/dev/ttyUSB0` with no file argument to make sure it can detect the SPI flash chip on the Chromebook through your Bus Pirate.
    If it reports an error or a generic chip, your clip is not on properly or is wired up wrong.
    If wired properly, it should find the GigaDevice chip:
    If wired properly, it should find the GigaDevice chip.
    If it reports an error or a generic chip (`0x00`), your clip is not on properly or is wired up wrong.
    ````
    jcs@ubuntu:~/chros/flashrom-0.9.8$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0
    ~/chros/flashrom-0.9.8$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0
    flashrom v0.9.8-r1888 on Linux 3.19.0-25-generic (x86_64)
    flashrom is free software, get the source code at http://www.flashrom.org
  12. jcs revised this gist Sep 4, 2015. 1 changed file with 13 additions and 7 deletions.
    20 changes: 13 additions & 7 deletions asus c201.md
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    @@ -1,6 +1,6 @@
    ####Removing SPI write protection
    ####Disabling SPI write protection

    Put the machine in developer-mode:
    Put the Chromebook in developer-mode:
    - With machine powered off, hold down Esc and Refresh(F3) while hitting power button
    - At warning prompt, hit Control+D, then Enter at prompt about enabling developer mode
    - Machine will format itself
    @@ -42,7 +42,7 @@ It should report success. `flashrom --wp-status` should confirm that write prot

    ####Reflashing new coreboot/libreboot

    From the machine, make a backup of your entire ROM before doing anything, and `scp` it off the machine to somewhere else.
    From the Chromebook, make a backup of your entire ROM before doing anything, and `scp` it off the machine to some place else.

    ````
    # flashrom -r asus_c201_factory_flash.rom
    @@ -81,6 +81,9 @@ area_offset="0x00300000" area_size="0x00100000" area_name="RW_LEGACY" area_flags
    #####Compile your coreboot/libreboot:
    You'll need a separate build machine for this.
    I used a 10G Ubuntu 14 virtual machine in VMware.
    TODO
    #####Preparing the new image to write
    @@ -144,8 +147,11 @@ Connect pins from Bus Pirate to test clip. The SPI chip pins are as follows, wi
    - Bus Pirate CS -> SPI pin 1 (CS)
    - Bus Pirate MISO -> SPI pin 2 (MISO)
    Once wired up, run `flashrom` with no file argument (just the programmer type) to make sure it can detect the chip.
    If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:
    If your build machine doesn't have it already, install flashrom (`apt-get install flashrom` on Ubuntu).
    Once wired up, run `flashrom -p buspirate_spi:dev=/dev/ttyUSB0` with no file argument to make sure it can detect the SPI flash chip on the Chromebook through your Bus Pirate.
    If it reports an error or a generic chip, your clip is not on properly or is wired up wrong.
    If wired properly, it should find the GigaDevice chip:
    ````
    jcs@ubuntu:~/chros/flashrom-0.9.8$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0
    @@ -159,11 +165,11 @@ No operations were specified.
    Now just flash the backup you made before reflashing.
    `sudo ./flashrom -w asus_c201_factory_flash.rom -p buspirate_spi:dev=/dev/ttyUSB0`
    `sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w asus_c201_factory_flash.rom`
    If you lost your backup, you can download the backup I made, but no guarantees that it will work on your machine:
    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - `e4478311e77745a1aff0a1117cc65010`
    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - MD5 `e4478311e77745a1aff0a1117cc65010`
    If all went well, after about 10 minutes of erasing and flashing, it should report success.
    Remove the test clip, reattach the battery, plug the power cable in, and it should boot to the Chrome "OS verification is OFF" screen.
  13. jcs revised this gist Sep 4, 2015. 1 changed file with 23 additions and 3 deletions.
    26 changes: 23 additions & 3 deletions asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -42,15 +42,14 @@ It should report success. `flashrom --wp-status` should confirm that write prot

    ####Reflashing new coreboot/libreboot

    Make a backup of your entire ROM before doing anything, and `scp` it off the machine to somewhere else.
    From the machine, make a backup of your entire ROM before doing anything, and `scp` it off the machine to somewhere else.

    ````
    # flashrom -r asus_c201_factory_flash.rom
    flashrom v0.9.4 : 15e4dc9 : Apr 02 2015 22:53:02 UTC on Linux 3.14.0 (armv7l), built with libpci 3.1.10, GCC 4.9.x-google 20150123 (prerelease), little endian
    Reading flash... SUCCESS
    ````

    Make a couple backups and check the `md5sum` values to make sure they're the same.
    `fmap_decode` will show how the ROM is layed out:

    ```
    @@ -80,10 +79,31 @@ area_offset="0x002f8000" area_size="0x00008000" area_name="RW_VPD" area_flags_ra
    area_offset="0x00300000" area_size="0x00100000" area_name="RW_LEGACY" area_flags_raw="0x01" area_flags="static"
    ````
    Compile your coreboot/libreboot:
    #####Compile your coreboot/libreboot:
    TODO
    #####Preparing the new image to write
    Only the first megabyte of your new coreboot ROM will be used, so you need to copy the other ~3 megs from the backup.
    From your build machine:
    ````
    ~/chros/coreboot$ dd if=build/coreboot.rom bs=1024 count=1024 of=firstmeg.rom
    ~/chros/coreboot$ dd if=asus_c201_factory_flash.rom bs=1024 skip=1024 of=latermegs.rom
    ~/chros/coreboot$ cat firstmeg.rom latermegs.rom > final.rom
    ````
    You can verify with `fmap_decode` that your new ROM still looks like the old one.
    Now `scp` it to your Chromebook and flash it:
    ````
    # flashrom -w final.rom
    ````
    Reboot and hope it works.
    ####Unbricking
    If your flashing went bad, you'll be unable to boot.
  14. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 0 deletions.
    1 change: 1 addition & 0 deletions asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -150,5 +150,6 @@ Remove the test clip, reattach the battery, plug the power cable in, and it shou
    ####References
    - https://lists.nongnu.org/archive/html/libreboot-dev/2015-08/msg00001.html
    - http://www.tnhh.net/2014/08/25/unbricking-chromebook-with-beaglebone.html
    - http://selinuxproject.org/~jmorris/lss2013_slides/safford_chromebook_takeown.pdf
  15. jcs revised this gist Sep 4, 2015. 1 changed file with 3 additions and 2 deletions.
    5 changes: 3 additions & 2 deletions asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -124,7 +124,8 @@ Connect pins from Bus Pirate to test clip. The SPI chip pins are as follows, wi
    - Bus Pirate CS -> SPI pin 1 (CS)
    - Bus Pirate MISO -> SPI pin 2 (MISO)
    Once wired up, run `flashrom` with no file argument (just the programmer type) to make sure it can detect the chip. If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:
    Once wired up, run `flashrom` with no file argument (just the programmer type) to make sure it can detect the chip.
    If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:
    ````
    jcs@ubuntu:~/chros/flashrom-0.9.8$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0
    @@ -144,7 +145,7 @@ If you lost your backup, you can download the backup I made, but no guarantees t
    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - `e4478311e77745a1aff0a1117cc65010`
    If all went well, after about 10 minutes of erasing and flashing, it should report success.
    If all went well, after about 10 minutes of erasing and flashing, it should report success.
    Remove the test clip, reattach the battery, plug the power cable in, and it should boot to the Chrome "OS verification is OFF" screen.
  16. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion asus c201.md
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    @@ -87,7 +87,7 @@ TODO
    ####Unbricking
    If your flashing went bad, you'll be unable to boot.
    To fix this, you'll have to reflash your backup from another machine.
    To fix this, you'll have to reflash your backup from another machine.
    You can do this fairly easily with a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    a [SOIC8/SOP8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.
  17. jcs revised this gist Sep 4, 2015. 1 changed file with 13 additions and 6 deletions.
    19 changes: 13 additions & 6 deletions asus c201.md
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    @@ -13,11 +13,14 @@ Flip powered-off machine over and remove 8 philips-head screws. 2 are located u

    ![https://i.imgur.com/o76SuTyl.jpg](https://i.imgur.com/o76SuTyl.jpg)

    With a plastic spudger/guitar pick, separate the black case from the silver keyboard/trackpad tray. Slide the spudger along the outer seam to separate it (you'll hear a bunch of clicks).
    With a plastic spudger/guitar pick, separate the blue case from the silver keyboard/trackpad tray.
    Slide the spudger along the outer seam to separate it (you'll hear a bunch of clicks).

    *Don't pull the bottom piece off or you'll pull out the cables to the keyboard.*

    Once the bottom piece is completely separated, flip the laptop over and open the lid. The keyboard should be loose. Pick it up just enough to flip it over without separating the cables.
    Once the bottom piece is completely separated, flip the laptop over and open the lid.
    The keyboard should be loose.
    Pick it up just enough to flip it over without separating the cables.

    Locate the write-protect screw on the left side (highlighted in red here).

    @@ -27,9 +30,11 @@ Remove the screw.

    ![https://i.imgur.com/H6caZiSl.jpg](https://i.imgur.com/H6caZiSl.jpg)

    Flip the keyboard back over so you can type, and power the machine on. Hit Control+D at the boot screen.
    Flip the keyboard back over so you can type, and power the machine on.
    Hit Control+D at the boot screen.

    Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo sh`, and `flashrom --wp-disable`. It should report success. `flashrom --wp-status` should confirm that write protection is disabled.
    Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo sh`, and `flashrom --wp-disable`.
    It should report success. `flashrom --wp-status` should confirm that write protection is disabled.

    ![https://i.imgur.com/NzYNPzml.jpg](https://i.imgur.com/NzYNPzml.jpg)

    @@ -87,11 +92,13 @@ You can do this fairly easily with a [Bus Pirate](http://www.amazon.com/SparkFun
    a [SOIC8/SOP8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.
    Use the instructions above to remove the keyboard. Remove the 8 or so screws holding the large heatsink to the case over the motherboard, exposing the battery connector. Unplug the battery.
    Use the instructions above to remove the keyboard.
    Remove the 8 or so screws holding the large heatsink to the case over the motherboard, exposing the battery connector.
    Unplug the battery.
    ![http://i.imgur.com/TzjWRODl.jpg](http://i.imgur.com/TzjWRODl.jpg)
    Attach your test clip to the flash chip located just to the left of the write-protect screw, noting pin 1 is in the lower left as looking at it from the front of the laptop (there is a dot on the lower left corner of the chip marking pin 1).
    Attach your test clip to the flash chip located just to the left of the write-protect screw, noting the dot on the lower left of the chip marking pin 1.
    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)
  18. jcs revised this gist Sep 4, 2015. 1 changed file with 6 additions and 1 deletion.
    7 changes: 6 additions & 1 deletion asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -138,4 +138,9 @@ If you lost your backup, you can download the backup I made, but no guarantees t
    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - `e4478311e77745a1aff0a1117cc65010`
    If all went well, after about 10 minutes of erasing and flashing, it should report success.
    Remove the test clip, reattach the battery, plug the power cable in, and it should boot to the Chrome "OS verification is OFF" screen.
    Remove the test clip, reattach the battery, plug the power cable in, and it should boot to the Chrome "OS verification is OFF" screen.
    ####References
    - http://www.tnhh.net/2014/08/25/unbricking-chromebook-with-beaglebone.html
    - http://selinuxproject.org/~jmorris/lss2013_slides/safford_chromebook_takeown.pdf
  19. jcs revised this gist Sep 4, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -37,7 +37,7 @@ Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo

    ####Reflashing new coreboot/libreboot

    Make a backup of your entire ROM before doing anything:
    Make a backup of your entire ROM before doing anything, and `scp` it off the machine to somewhere else.

    ````
    # flashrom -r asus_c201_factory_flash.rom
  20. jcs revised this gist Sep 4, 2015. 1 changed file with 4 additions and 2 deletions.
    6 changes: 4 additions & 2 deletions asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -49,7 +49,7 @@ Make a couple backups and check the `md5sum` values to make sure they're the sam
    `fmap_decode` will show how the ROM is layed out:

    ```
    # fmap_decode bios.bin
    # fmap_decode asus_c201_factory_flash.rom
    fmap_signature="0x5f5f464d41505f5f" fmap_ver_major="1" fmap_ver_minor="0" fmap_base="0x0000000000000000" fmap_size="0x400000" fmap_name="FMAP" fmap_nareas="22"
    area_offset="0x00000000" area_size="0x00200000" area_name="WP_RO" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00000000" area_size="0x001f0000" area_name="RO_SECTION" area_flags_raw="0x01" area_flags="static"
    @@ -81,7 +81,9 @@ TODO
    ####Unbricking
    Get a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    If your flashing went bad, you'll be unable to boot.
    To fix this, you'll have to reflash your backup from another machine.
    You can do this fairly easily with a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    a [SOIC8/SOP8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.
  21. jcs revised this gist Sep 4, 2015. 1 changed file with 40 additions and 0 deletions.
    40 changes: 40 additions & 0 deletions asus c201.md
    View file
    Original file line number Diff line number Diff line change
    @@ -37,6 +37,46 @@ Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo

    ####Reflashing new coreboot/libreboot

    Make a backup of your entire ROM before doing anything:

    ````
    # flashrom -r asus_c201_factory_flash.rom
    flashrom v0.9.4 : 15e4dc9 : Apr 02 2015 22:53:02 UTC on Linux 3.14.0 (armv7l), built with libpci 3.1.10, GCC 4.9.x-google 20150123 (prerelease), little endian
    Reading flash... SUCCESS
    ````

    Make a couple backups and check the `md5sum` values to make sure they're the same.
    `fmap_decode` will show how the ROM is layed out:

    ```
    # fmap_decode bios.bin
    fmap_signature="0x5f5f464d41505f5f" fmap_ver_major="1" fmap_ver_minor="0" fmap_base="0x0000000000000000" fmap_size="0x400000" fmap_name="FMAP" fmap_nareas="22"
    area_offset="0x00000000" area_size="0x00200000" area_name="WP_RO" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00000000" area_size="0x001f0000" area_name="RO_SECTION" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00000000" area_size="0x00100000" area_name="COREBOOT" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00100000" area_size="0x00001000" area_name="FMAP" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00101000" area_size="0x000eef00" area_name="GBB" area_flags_raw="0x01" area_flags="static"
    area_offset="0x001eff00" area_size="0x00000100" area_name="RO_FRID" area_flags_raw="0x01" area_flags="static"
    area_offset="0x001f0000" area_size="0x00010000" area_name="RO_VPD" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00200000" area_size="0x00078000" area_name="RW_SECTION_A" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00200000" area_size="0x00002000" area_name="VBLOCK_A" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00202000" area_size="0x00056000" area_name="FW_MAIN_A" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00258000" area_size="0x0001ff00" area_name="EC_MAIN_A" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00277f00" area_size="0x00000100" area_name="RW_FWID_A" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00278000" area_size="0x00004000" area_name="RW_SHARED" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00278000" area_size="0x00004000" area_name="SHARED_DATA" area_flags_raw="0x01" area_flags="static"
    area_offset="0x0027c000" area_size="0x00004000" area_name="RW_ELOG" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00280000" area_size="0x00078000" area_name="RW_SECTION_B" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00280000" area_size="0x00002000" area_name="VBLOCK_B" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00282000" area_size="0x00056000" area_name="FW_MAIN_B" area_flags_raw="0x01" area_flags="static"
    area_offset="0x002d8000" area_size="0x0001ff00" area_name="EC_MAIN_B" area_flags_raw="0x01" area_flags="static"
    area_offset="0x002f7f00" area_size="0x00000100" area_name="RW_FWID_B" area_flags_raw="0x01" area_flags="static"
    area_offset="0x002f8000" area_size="0x00008000" area_name="RW_VPD" area_flags_raw="0x01" area_flags="static"
    area_offset="0x00300000" area_size="0x00100000" area_name="RW_LEGACY" area_flags_raw="0x01" area_flags="static"
    ````
    Compile your coreboot/libreboot:
    TODO
    ####Unbricking
  22. jcs revised this gist Sep 4, 2015. 1 changed file with 7 additions and 7 deletions.
    14 changes: 7 additions & 7 deletions asus c201.md
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    Original file line number Diff line number Diff line change
    @@ -53,7 +53,7 @@ Attach your test clip to the flash chip located just to the left of the write-pr

    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)

    Connect pins from Bus Pirate to test clip. The SPI chip pins are:
    Connect pins from Bus Pirate to test clip. The SPI chip pins are as follows, with the dot in the lower left.

    VCC
      | HOLD
    @@ -68,12 +68,12 @@ Connect pins from Bus Pirate to test clip. The SPI chip pins are:
    | MISO
      CS

    Bus Pirate GND -> SPI pin 4 (GND)
    Bus Pirate 3V3 -> SPI pin 8 (VLK)
    Bus Pirate CLK -> SPI pin 6 (SCLK)
    Bus Pirate MOSI -> SPI pin 5 (MOSI)
    Bus Pirate CS -> SPI pin 1 (CS)
    Bus Pirate MISO -> SPI pin 2 (MISO)
    - Bus Pirate GND -> SPI pin 4 (GND)
    - Bus Pirate 3V3 -> SPI pin 8 (VLK)
    - Bus Pirate CLK -> SPI pin 6 (SCLK)
    - Bus Pirate MOSI -> SPI pin 5 (MOSI)
    - Bus Pirate CS -> SPI pin 1 (CS)
    - Bus Pirate MISO -> SPI pin 2 (MISO)

    Once wired up, run `flashrom` with no file argument (just the programmer type) to make sure it can detect the chip. If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:

  23. jcs revised this gist Sep 4, 2015. 1 changed file with 9 additions and 8 deletions.
    17 changes: 9 additions & 8 deletions asus c201.md
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    @@ -1,4 +1,4 @@
    ###Removing SPI write protection
    ####Removing SPI write protection

    Put the machine in developer-mode:
    - With machine powered off, hold down Esc and Refresh(F3) while hitting power button
    @@ -35,21 +35,21 @@ Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo

    `halt -p` to power down, snap keyboard tray back in, put screws and rubber feet back.

    ###Reflashing new coreboot/libreboot
    ####Reflashing new coreboot/libreboot

    TODO

    ###Unbricking
    ####Unbricking

    Get a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    a [SOIC8/SOP8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.

    Remove 6 or so screws in large heatsink that attaches over motherboard, exposing the battery connector. Unplug the battery.
    Use the instructions above to remove the keyboard. Remove the 8 or so screws holding the large heatsink to the case over the motherboard, exposing the battery connector. Unplug the battery.

    ![http://i.imgur.com/TzjWRODl.jpg](http://i.imgur.com/TzjWRODl.jpg)

    Attach test clip to flash chip (located just to the left of the write-protect screw), noting pin 1 is in the lower left as looking down at it from the front of the laptop (there is a dot on the chip in that corner).
    Attach your test clip to the flash chip located just to the left of the write-protect screw, noting pin 1 is in the lower left as looking at it from the front of the laptop (there is a dot on the lower left corner of the chip marking pin 1).

    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)

    @@ -75,7 +75,7 @@ Bus Pirate MOSI -> SPI pin 5 (MOSI)
    Bus Pirate CS -> SPI pin 1 (CS)
    Bus Pirate MISO -> SPI pin 2 (MISO)

    Once wired up, run `flashrom` to make sure it can detect the chip. If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:
    Once wired up, run `flashrom` with no file argument (just the programmer type) to make sure it can detect the chip. If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:

    ````
    jcs@ubuntu:~/chros/flashrom-0.9.8$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0
    @@ -91,8 +91,9 @@ Now just flash the backup you made before reflashing.

    `sudo ./flashrom -w asus_c201_factory_flash.rom -p buspirate_spi:dev=/dev/ttyUSB0`

    If you lost your backup, you can download the backup I made:
    If you lost your backup, you can download the backup I made, but no guarantees that it will work on your machine:

    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - `e4478311e77745a1aff0a1117cc65010`

    If all went well (the process takes about 10 minutes), it will report success. Remove the test clip, hook the battery back up, plug the power back in, and it should boot to the Chrome "OS verification is OFF" screen.
    If all went well, after about 10 minutes of erasing and flashing, it should report success.
    Remove the test clip, reattach the battery, plug the power cable in, and it should boot to the Chrome "OS verification is OFF" screen.
  24. jcs revised this gist Sep 3, 2015. 1 changed file with 48 additions and 2 deletions.
    50 changes: 48 additions & 2 deletions asus c201.md
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    @@ -47,6 +47,52 @@ and some cables.

    Remove 6 or so screws in large heatsink that attaches over motherboard, exposing the battery connector. Unplug the battery.

    Attach test clip to flash chip (located just to the left of the write-protect screw), noting pin 1 is in the lower left as looking down at it from the front of the laptop.
    ![http://i.imgur.com/TzjWRODl.jpg](http://i.imgur.com/TzjWRODl.jpg)

    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)
    Attach test clip to flash chip (located just to the left of the write-protect screw), noting pin 1 is in the lower left as looking down at it from the front of the laptop (there is a dot on the chip in that corner).

    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)

    Connect pins from Bus Pirate to test clip. The SPI chip pins are:

    VCC
      | HOLD
      | | SCLK
      8 7 6 5-MOSI
     +-------+
     |       |
     |o      |
     +-------+
      1 2 3 4-GND
    | | WP
    | MISO
      CS

    Bus Pirate GND -> SPI pin 4 (GND)
    Bus Pirate 3V3 -> SPI pin 8 (VLK)
    Bus Pirate CLK -> SPI pin 6 (SCLK)
    Bus Pirate MOSI -> SPI pin 5 (MOSI)
    Bus Pirate CS -> SPI pin 1 (CS)
    Bus Pirate MISO -> SPI pin 2 (MISO)

    Once wired up, run `flashrom` to make sure it can detect the chip. If it reports an error or a generic chip, your clip is not on properly or is wired up wrong. If wired properly, it should find the GigaDevice chip:

    ````
    jcs@ubuntu:~/chros/flashrom-0.9.8$ sudo ./flashrom -p buspirate_spi:dev=/dev/ttyUSB0
    flashrom v0.9.8-r1888 on Linux 3.19.0-25-generic (x86_64)
    flashrom is free software, get the source code at http://www.flashrom.org
    Calibrating delay loop... delay loop is unreliable, trying to continue OK.
    Found GigaDevice flash chip "GD25Q32(B)" (4096 kB, SPI) on buspirate_spi.
    No operations were specified.
    ````

    Now just flash the backup you made before reflashing.

    `sudo ./flashrom -w asus_c201_factory_flash.rom -p buspirate_spi:dev=/dev/ttyUSB0`

    If you lost your backup, you can download the backup I made:

    [https://jcs.org/tmp/asus_c201_factory_flash.rom](https://jcs.org/tmp/asus_c201_factory_flash.rom) - `e4478311e77745a1aff0a1117cc65010`

    If all went well (the process takes about 10 minutes), it will report success. Remove the test clip, hook the battery back up, plug the power back in, and it should boot to the Chrome "OS verification is OFF" screen.
  25. jcs renamed this gist Sep 3, 2015. 1 changed file with 0 additions and 0 deletions.
    0 asus c201 → asus c201.md
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    File renamed without changes.
  26. jcs renamed this gist Sep 3, 2015. 1 changed file with 19 additions and 1 deletion.
    20 changes: 19 additions & 1 deletion wpscrew.md → asus c201
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    @@ -1,3 +1,5 @@
    ###Removing SPI write protection

    Put the machine in developer-mode:
    - With machine powered off, hold down Esc and Refresh(F3) while hitting power button
    - At warning prompt, hit Control+D, then Enter at prompt about enabling developer mode
    @@ -31,4 +33,20 @@ Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo

    ![https://i.imgur.com/NzYNPzml.jpg](https://i.imgur.com/NzYNPzml.jpg)

    `halt -p` to power down, snap keyboard tray back in, put screws and rubber feet back.
    `halt -p` to power down, snap keyboard tray back in, put screws and rubber feet back.

    ###Reflashing new coreboot/libreboot

    TODO

    ###Unbricking

    Get a [Bus Pirate](http://www.amazon.com/SparkFun-Bus-Pirate/dp/B004G2F6H0),
    a [SOIC8/SOP8 test clip](http://www.amazon.com/Signstek-SOIC8-Socket-Adpter-Programmer/dp/B00V9QNAC4),
    and some cables.

    Remove 6 or so screws in large heatsink that attaches over motherboard, exposing the battery connector. Unplug the battery.

    Attach test clip to flash chip (located just to the left of the write-protect screw), noting pin 1 is in the lower left as looking down at it from the front of the laptop.

    ![http://i.imgur.com/MOQDeK0l.jpg](http://i.imgur.com/MOQDeK0l.jpg)
  27. jcs revised this gist Aug 25, 2015. 1 changed file with 4 additions and 4 deletions.
    8 changes: 4 additions & 4 deletions wpscrew.md
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    @@ -21,13 +21,13 @@ Locate the write-protect screw on the left side (highlighted in red here).

    ![https://i.imgur.com/NWCJu1nl.jpg](https://i.imgur.com/NWCJu1nl.jpg)

    ![https://i.imgur.com/H6caZiSl.jpg](https://i.imgur.com/H6caZiSl.jpg)
    Remove the screw.

    Remove the screw, flip the keyboard back over so you can type, and power the machine on.
    ![https://i.imgur.com/H6caZiSl.jpg](https://i.imgur.com/H6caZiSl.jpg)

    Sign-in as guest, Control+Alt+T to open `crosh`, then `shell`, `sudo sh`, and `flashrom --wp-disable`. It should report success.
    Flip the keyboard back over so you can type, and power the machine on. Hit Control+D at the boot screen.

    `flashrom --wp-status` should confirm that write protection is disabled.
    Click "Sign-in as guest", hit Control+Alt+T to open `crosh`, then `shell`, `sudo sh`, and `flashrom --wp-disable`. It should report success. `flashrom --wp-status` should confirm that write protection is disabled.

    ![https://i.imgur.com/NzYNPzml.jpg](https://i.imgur.com/NzYNPzml.jpg)

  28. jcs revised this gist Aug 25, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion wpscrew.md
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    @@ -11,7 +11,7 @@ Flip powered-off machine over and remove 8 philips-head screws. 2 are located u

    ![https://i.imgur.com/o76SuTyl.jpg](https://i.imgur.com/o76SuTyl.jpg)

    With a plastic spudger/guitar pick, separate the case along the black (case) and silver (keyboard/trackpad) parts.
    With a plastic spudger/guitar pick, separate the black case from the silver keyboard/trackpad tray. Slide the spudger along the outer seam to separate it (you'll hear a bunch of clicks).

    *Don't pull the bottom piece off or you'll pull out the cables to the keyboard.*

  29. jcs revised this gist Aug 25, 2015. 1 changed file with 1 addition and 1 deletion.
    2 changes: 1 addition & 1 deletion wpscrew.md
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    @@ -1,6 +1,6 @@
    Put the machine in developer-mode:
    - With machine powered off, hold down Esc and Refresh(F3) while hitting power button
    - At warning prompt, hit Control+D, then Enter to prompt about enabling developer mode
    - At warning prompt, hit Control+D, then Enter at prompt about enabling developer mode
    - Machine will format itself

    Now remove the write-protect screw to enable `flashrom` to flash new Coreboot/Libreboot.
  30. jcs revised this gist Aug 25, 2015. 1 changed file with 7 additions and 2 deletions.
    9 changes: 7 additions & 2 deletions wpscrew.md
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    @@ -1,6 +1,11 @@
    Put the machine in developer-mode.
    Put the machine in developer-mode:
    - With machine powered off, hold down Esc and Refresh(F3) while hitting power button
    - At warning prompt, hit Control+D, then Enter to prompt about enabling developer mode
    - Machine will format itself

    Power machine off, flip over and remove 8 philips-head screws. 2 are located under rubber feet.
    Now remove the write-protect screw to enable `flashrom` to flash new Coreboot/Libreboot.

    Flip powered-off machine over and remove 8 philips-head screws. 2 are located under rubber feet.

    ![https://i.imgur.com/zlA6JsFl.jpg](https://i.imgur.com/zlA6JsFl.jpg)