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This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -43,6 +43,14 @@ def __init__(self, fifo_depth=256): def elaborate(self, platform): m = Module() # This implementation improves resource use efficiency by merging the two memories that # would otherwise be necessary in a typical implementation: the FIFO for buffering packet # data, and the lookahead memory for COBS encoding. Specifically, it reuses the "empty" # space in the FIFO for storing bytes that follow a yet-unknown COBS overhead byte; this is # called "staging". Once the value of the overhead byte becomes known, the FIFO write # pointer is advanced simultaneously with the overhead byte being overwriten; this is # called "committing". m.submodules.data = data = memory.Memory(shape=8, depth=self.fifo_depth, init=[]) w_port = data.write_port() r_port = data.read_port(transparent_for=(w_port,)) -
May 10, 2025 . 1 changed file with 2 additions and 8 deletions.There are no files selected for viewing
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -43,8 +43,7 @@ async def testbench_o(ctx): sim.add_clock(1e-6) sim.add_testbench(testbench_i) sim.add_testbench(testbench_o) sim.run() return data_o @@ -79,8 +78,7 @@ async def testbench_o(ctx): sim.add_clock(1e-6) sim.add_testbench(testbench_i) sim.add_testbench(testbench_o) sim.run() return data_o @@ -119,10 +117,6 @@ def test_decoder_vmlinuz(): assert rtl_decode(cobs.encode(vmlinuz) + b"\0") == [vmlinuz] vmlinuz = bytes.fromhex(""" 4d5a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000cd238281400000005045000064860400000000000000000001000000a00006020b02021400d0b70000700600 -
May 10, 2025 . 2 changed files with 15 additions and 12 deletions.There are no files selected for viewing
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -11,14 +11,18 @@ class Encoder(wiring.Component): The encoder accepts a stream of tokens, which can be either _data_ or _end_, and produces a stream of bytes. Input data tokens produce non-NUL output bytes with a maximum latency of 256 cycles; input end tokens produce NUL output bytes. Since COBS encoding requires up to 254 bytes of lookahead, and a COBS encoder will be usually combined with a FIFO (either at the input or at the output), this encoder is combined with a FIFO to use limited memory resources more efficiently. All but one byte of the internal FIFO will be filled with data in case of output back-pressure. The latency of the encoder depends on the type and value of input tokens. Input non-NUL data tokens do not immediately produce output bytes; rather, bytes corresponding to these tokens appear at the output only after: (a) an input end token, or (b) an input NUL data token, or (c) 255th consecutive non-NUL data token. .. _cobs: https://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing """ @@ -53,7 +57,7 @@ def write(at, data): m.d.comb += w_port.data.eq(data) m.d.comb += w_port.en.eq(1) staged = Signal(8, init=1) def stage(data): write(w_addr + staged, data) @@ -62,13 +66,9 @@ def stage(data): def commit(): write(w_addr, staged) m.d.sync += w_addr.eq(w_addr + staged) m.d.sync += staged.eq(1) with m.FSM(): with m.State("Data"): with m.If(self.i.valid & ~full): with m.If(self.i.p.end): @@ -77,19 +77,17 @@ def commit(): m.next = "End" with m.Elif(staged == 0xff): commit() with m.Elif(self.i.p.data == 0x00): m.d.comb += self.i.ready.eq(1) commit() with m.Else(): m.d.comb += self.i.ready.eq(1) stage(self.i.p.data) with m.State("End"): write(w_addr, 0x00) m.d.sync += w_addr.eq(w_addr + 1) m.next = "Data" m.d.comb += self.o.valid.eq(~empty) m.d.comb += self.o.payload.eq(r_port.data) This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -43,7 +43,8 @@ async def testbench_o(ctx): sim.add_clock(1e-6) sim.add_testbench(testbench_i) sim.add_testbench(testbench_o) with sim.write_vcd("test.vcd"): sim.run() return data_o @@ -118,6 +119,10 @@ def test_decoder_vmlinuz(): assert rtl_decode(cobs.encode(vmlinuz) + b"\0") == [vmlinuz] def test_encoder_zeros(): rtl_encode(b"\0" * 200 + b"$") vmlinuz = bytes.fromhex(""" 4d5a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000cd238281400000005045000064860400000000000000000001000000a00006020b02021400d0b70000700600 -
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This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -0,0 +1,166 @@ from amaranth import * from amaranth.lib import data, wiring, memory, stream from amaranth.lib.stream import In, Out __all__ = ["Encoder", "Decoder"] class Encoder(wiring.Component): """`Consistent Overhead Byte Stuffing <cobs>`_ encoder combined with a FIFO. The encoder accepts a stream of tokens, which can be either _data_ or _end_, and produces a stream of bytes. Input data tokens produce non-NUL output bytes with a maximum latency of 256 cycles; input end tokens produce NUL output bytes and ensure that all preceding data is flushed via the output stream. Since COBS encoding requires up to 254 bytes of lookahead, and a COBS encoder will be usually combined with a FIFO (either at the input or at the output), this encoder is combined with a FIFO to use limited memory resources more efficiently. All but one byte of the internal FIFO will be filled with data in case of output back-pressure. .. _cobs: https://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing """ i: In(stream.Signature(data.StructLayout({ "data": 8, "end": 1 }))) o: Out(stream.Signature(8)) def __init__(self, fifo_depth=256): if not (fifo_depth >= 256 and fifo_depth.bit_count() == 1): raise ValueError("COBS encoder requires a power-of-2 sized FIFO that is " "at least 256 bytes deep") self.fifo_depth = fifo_depth super().__init__() def elaborate(self, platform): m = Module() m.submodules.data = data = memory.Memory(shape=8, depth=self.fifo_depth, init=[]) w_port = data.write_port() r_port = data.read_port(transparent_for=(w_port,)) w_addr = Signal.like(w_port.addr) r_addr = Signal.like(r_port.addr) empty = (w_addr == r_addr) full = (w_addr == r_addr - 1) def write(at, data): m.d.comb += w_port.addr.eq(at) m.d.comb += w_port.data.eq(data) m.d.comb += w_port.en.eq(1) staged = Signal(8) def stage(data): write(w_addr + staged, data) m.d.sync += staged.eq(staged + 1) def commit(): write(w_addr, staged) m.d.sync += w_addr.eq(w_addr + staged) m.d.sync += staged.eq(0) with m.FSM(): with m.State("Start"): stage(0x00) m.next = "Data" with m.State("Data"): with m.If(self.i.valid & ~full): with m.If(self.i.p.end): m.d.comb += self.i.ready.eq(1) commit() m.next = "End" with m.Elif(staged == 0xff): commit() m.next = "Start" with m.Elif(self.i.p.data == 0x00): m.d.comb += self.i.ready.eq(1) commit() m.next = "Start" with m.Else(): m.d.comb += self.i.ready.eq(1) stage(self.i.p.data) with m.State("End"): write(w_addr, 0x00) m.d.sync += w_addr.eq(w_addr + 1) m.next = "Start" m.d.comb += self.o.valid.eq(~empty) m.d.comb += self.o.payload.eq(r_port.data) with m.If(self.o.valid & self.o.ready): m.d.comb += r_port.addr.eq(r_addr + 1) m.d.sync += r_addr.eq(r_addr + 1) with m.Else(): m.d.comb += r_port.addr.eq(r_addr) return m class Decoder(wiring.Component): """`Consistent Overhead Byte Stuffing <cobs>`_ decoder. Performs an inversion of the transformation done by :class:`Encoder` with a fixed 0 cycle latency. If invalid COBS data is encountered (namely: if a group header byte or data byte is NUL), the decoder transitions to an error state, signaled by the ``error`` output. This state is final, cleared only by a reset. .. _cobs: https://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing """ i: In(stream.Signature(8)) o: Out(stream.Signature(data.StructLayout({ "data": 8, "end": 1 }))) error: Out(1) def elaborate(self, platform): m = Module() count = Signal(8) offset = Signal(8) with m.FSM(): with m.State("Start"): m.d.comb += self.i.ready.eq(1) with m.If(self.i.valid & self.i.ready): m.d.sync += count.eq(1) with m.If(self.i.payload != 0x00): m.d.sync += offset.eq(self.i.payload) m.next = "Data" with m.Else(): m.next = "Error" with m.State("Data"): m.d.comb += self.i.ready.eq(self.o.ready) with m.If(self.i.valid & self.i.ready): with m.If(offset == count): m.d.sync += count.eq(1) with m.If(self.i.payload == 0x00): m.d.comb += self.o.payload.end.eq(1) m.d.comb += self.o.valid.eq(1) m.next = "Start" with m.Else(): m.d.comb += self.o.payload.data.eq(0x00) m.d.comb += self.o.valid.eq(offset != 0xff) m.d.sync += offset.eq(self.i.payload) with m.Else(): m.d.sync += count.eq(count + 1) with m.If(self.i.payload != 0x00): m.d.comb += self.o.payload.data.eq(self.i.payload) m.d.comb += self.o.valid.eq(1) with m.Else(): m.next = "Error" with m.State("Error"): m.d.comb += self.error.eq(1) return m This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -0,0 +1,303 @@ from amaranth import * from amaranth.sim import Simulator from amaranth_cobs import * from cobs import cobs def ref_encode(data_i: bytes) -> bytes: return b"\0".join(cobs.encode(chunk) if chunk else b"" for chunk in data_i.split(b"$")) def rtl_encode(data_i: bytes, dollar=True) -> bytes: dut = Encoder() async def testbench_i(ctx): ctx.set(dut.i.valid, 1) for byte in data_i: if byte == ord("$") and dollar: ctx.set(dut.i.payload, {"end": 1}) else: ctx.set(dut.i.payload, {"data": byte}) await ctx.tick().until(dut.i.ready) if not dollar: ctx.set(dut.i.payload, {"end": 1}) await ctx.tick().until(dut.i.ready) ctx.set(dut.i.valid, 0) data_o = bytearray() async def testbench_o(ctx): ctx.set(dut.o.ready, 1) empty_for = 0 while empty_for < len(data_i) + 3: _, _, valid, payload = await ctx.tick().sample(dut.o.valid).sample(dut.o.payload) if valid: data_o.append(payload) empty_for = 0 else: empty_for += 1 ctx.set(dut.o.ready, 0) sim = Simulator(dut) sim.add_clock(1e-6) sim.add_testbench(testbench_i) sim.add_testbench(testbench_o) sim.run() return data_o def rtl_decode(data_i: bytes, dollar=True) -> bytes: dut = Decoder() async def testbench_i(ctx): ctx.set(dut.i.valid, 1) for byte in data_i: ctx.set(dut.i.payload, byte) await ctx.tick().until(dut.i.ready) ctx.set(dut.i.valid, 0) data_o = [] async def testbench_o(ctx): pending = bytearray() ctx.set(dut.o.ready, 1) for _ in range(data_i.count(b"\0")): while True: _, _, valid, payload = await ctx.tick().sample(dut.o.valid).sample(dut.o.payload) if valid: if payload.end: data_o.append(bytes(pending)) pending.clear() break else: pending.append(payload.data) ctx.set(dut.o.ready, 0) sim = Simulator(dut) sim.add_clock(1e-6) sim.add_testbench(testbench_i) sim.add_testbench(testbench_o) with sim.write_vcd("test.vcd"): sim.run() return data_o def cases() -> list[bytes]: return [ b"\0$", b"\0\0$", b"\0A\0$", b"AB\0C$", b"ABCD$", b"A\0\0\0$", b"A"*254+b"$", b"\0"+b"A"*254+b"$", b"A"*500+b"$", b"foo$bar$", ] def test_encoder_simple(): for case in cases(): assert rtl_encode(case) == ref_encode(case) def test_encoder_vmlinuz(): assert rtl_encode(vmlinuz, dollar=False) == cobs.encode(vmlinuz) + b"\0" def test_decoder_simple(): for case in cases(): print(ref_encode(case)) assert rtl_decode(ref_encode(case)) == case.split(b"$")[:-1] def test_decoder_vmlinuz(): assert rtl_decode(cobs.encode(vmlinuz) + b"\0") == [vmlinuz] vmlinuz = bytes.fromhex(""" 4d5a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000cd238281400000005045000064860400000000000000000001000000a00006020b02021400d0b70000700600 00000000fd5cb7000050000000000000000000000010000000020000000000000300000000000000000000000090be000010 00001a42b8000a00000100000000000000000000000000000000000000000000000000000000000000000000000006000000 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